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81. 发明授权

US06222215B1 DRAM circuitry 失效
标题翻译： DRAM电路
公开(公告)号：US06222215B1
公开(公告)日：2001-04-24
申请号：US08935836
申请日：1997-09-23
申请人： John K. Zahurak
发明人： John K. Zahurak
IPC分类号： H01L27108
CPC分类号： H01L27/10835 , H01L27/10852 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/1203 , H01L28/91
摘要： Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer. In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate. According to another aspect of the invention, adjacent word lines are formed over the first insulating layer and source/drain diffusion regions are formed within the semiconductive material laterally outward of the word lines. Respective capacitor containers are etched into the diffusion regions and capacitors are formed within the etched containers. In a preferred implementation, storage node material which constitutes part of the capacitors is in electrical contact with the respective diffusion regions and comprises part of a DRAM memory cell.
摘要翻译：描述形成电容器和相关集成电路的方法。在优选实施例中，电容器形成动态随机存取存储器（DRAM）单元的一部分。根据本发明的一个方面，在半导体材料层上形成第一绝缘层。在半导体材料层上形成导电栅极。在栅极上形成第二绝缘层，然后蚀刻以形成电容器容器。在一个实施方案中，进行这种蚀刻以向外暴露半导体材料层。在另一个实施方案中，这种蚀刻继续进入半导体材料层。在又一实施方案中，这种蚀刻完全通过半导体材料层进入第一绝缘层。在优选的实施方式中，在电容器容器内形成存储电容器，该电容器容器在栅极的正上方和正下方延伸。根据本发明的另一方面，在第一绝缘层之上形成相邻字线，并且源/漏扩散区形成在字线的横向外侧的半导体材料内。相应的电容器容器被蚀刻到扩散区域中，并且在蚀刻的容器内形成电容器。在优选的实施方案中，构成电容器的一部分的存储节点材料与相应的扩散区电接触并且包括DRAM存储单元的一部分。

82. 发明授权

US06174806B1 High pressure anneals of integrated circuit structures 失效
公开(公告)号：US06174806B1
公开(公告)日：2001-01-16
申请号：US08790279
申请日：1997-01-28
申请人： Randhir P. S. Thakur , John K. Zahurak
发明人： Randhir P. S. Thakur , John K. Zahurak
IPC分类号： H01L2144
CPC分类号： H01L21/76856 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76882 , Y10S438/909
摘要： According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention. In further embodiments, dielectrics deposited between conductive layers are reflowed at high pressure and low temperature. Still further, multiple metalized layers are connected by vias filled with conductive material using high pressure and low temperature.

83. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

84. 发明授权

US6060355A Process for improving roughness of conductive layer 失效
标题翻译：改善导电层粗糙度的工艺
公开(公告)号：US6060355A
公开(公告)日：2000-05-09
申请号：US73380
申请日：1998-05-06
申请人： Shubneesh Batra , Pierre C. Fazan , John K. Zahurak
发明人： Shubneesh Batra , Pierre C. Fazan , John K. Zahurak
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20 , H01L21/8249 , H01L27/108
CPC分类号： H01L28/84 , Y10S438/964
摘要： Disclosed is a method of fabricating hemispherical grained (HSG) silicon layers. A surface seeding method is disclosed, wherein an amorphous silicon layer is doped with germanium. The silicon may be doped with germanium during deposition, or a previously formed silicon layer may be implanted with the germanium. The layer may also be in situ conductively doped. The Ge-doped amorphous silicon is then subjected to a vacuum anneal in which surface migration of silicon atoms causes a redistribution in the layer, and hemispherical grains or bumps result. A seeding source gas may flow during the anneal to aid in nucleation. The method permits HSG silicon formation at lower temperature and shorter duration anneals than prior art methods. Greater silicon mobility in the presence of germanium dopants also enables the growth of larger grains, thus enhancing surface area. At the same time, the germanium provides conductivity for memory cell charge storage.
摘要翻译：公开了一种制造半球形颗粒（HSG）硅层的方法。公开了一种表面接种方法，其中非晶硅层掺杂有锗。在沉积期间硅可以掺杂锗，或者可以用锗注入预先形成的硅层。该层也可以是原位导电掺杂的。然后对Ge掺杂的非晶硅进行真空退火，其中硅原子的表面迁移导致该层中的再分布，并且产生半球形晶粒或凸起。在退火期间，晶种源气体可以流动以帮助成核。该方法允许在较低温度下HSG硅的形成和比现有技术方法更短的持续时间退火。在锗掺杂剂存在的情况下，更大的硅迁移率也使得能够生长较大的晶粒，从而增强了表面积。同时，锗为记忆体电荷存储提供电导率。

85. 发明授权

US5770500A Process for improving roughness of conductive layer 失效
公开(公告)号：US5770500A
公开(公告)日：1998-06-23
申请号：US749569
申请日：1996-11-15
申请人： Shubneesh Batra , Pierre C. Fazan , John K. Zahurak
发明人： Shubneesh Batra , Pierre C. Fazan , John K. Zahurak
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L28/84 , Y10S438/964
摘要： Disclosed is a method of fabricating hemispherical grained (HSG) silicon layers. A surface seeding method is disclosed, wherein an amorphous silicon layer is doped with germanium. The silicon may be doped with germanium during deposition, or a previously formed silicon layer may be implanted with the germanium. The layer may also be in situ conductively doped. The Ge-doped amorphous silicon is then subjected to a vacuum anneal in which surface migration of silicon atoms causes a redistribution in the layer, and hemispherical grains or bumps result. A seeding source gas may flow during the anneal to aid in nucleation. The method permits HSG silicon formation at lower temperature and shorter duration anneals than prior art methods. Greater silicon mobility in the presence of germanium dopants also enables the growth of larger grains, thus enhancing surface area. At the same time, the germanium provides conductivity for memory cell charge storage.

86. 发明授权

US08921906B2 Disposable pillars for contact formation 有权
标题翻译：接触形成的一次性支柱
公开(公告)号：US08921906B2
公开(公告)日：2014-12-30
申请号：US13282671
申请日：2011-10-27
申请人： Byron Neville Burgess , John K. Zahurak
发明人： Byron Neville Burgess , John K. Zahurak
IPC分类号： H01L27/108 , H01L29/94 , H01L21/768 , H01L27/02
CPC分类号： H01L21/76897 , H01L21/0332 , H01L21/31055 , H01L21/31116 , H01L21/3212 , H01L21/823475 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/1052 , H01L27/1085 , H01L27/10888 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
摘要翻译：公开了用于在集成电路中形成触点的牺牲插头以及在集成电路阵列中形成连接的方法。可以使用各种图案转移和蚀刻步骤来创建密集堆叠的特征以及特征之间的连接。牺牲材料可以以跨越字线的连续的之字形线图案被图案化。平面化可以产生平行四边形的材料块，其可以覆盖有源区域以形成牺牲插塞，其可以用导电材料代替以形成接触。

87. 发明授权

US08735862B2 Memory cells, methods of forming memory cells and methods of forming memory arrays 有权
标题翻译：存储单元，形成存储单元的方法和形成存储器阵列的方法
公开(公告)号：US08735862B2
公开(公告)日：2014-05-27
申请号：US13084011
申请日：2011-04-11
申请人： Jun Liu , John K. Zahurak
发明人： Jun Liu , John K. Zahurak
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.
摘要翻译：一些实施例包括在一对电极之间具有多个可编程材料结构的存储器单元。可编程材料结构之一具有第一边缘，另一个可编程材料结构具有接触第一边缘的第二边缘。一些实施例包括形成存储器单元阵列的方法。第一可编程材料段形成在底部电极上。第一可编程材料段沿第一轴线延伸。第二可编程材料的线形成在第一可编程材料段上，并且形成为沿与第一轴相交的第二轴线延伸。第二可编程材料线具有接触第一可编程材料段的上表面的下表面。顶部电极线形成在第二可编程材料线上。

88. 发明申请

US20120097913A1 Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell 有权
标题翻译：包含非易失性存储器单元的集成电路和形成非易失性存储器单元的方法
公开(公告)号：US20120097913A1
公开(公告)日：2012-04-26
申请号：US12909650
申请日：2010-10-21
申请人： Jun Liu , John K. Zahurak
发明人： Jun Liu , John K. Zahurak
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1266 , H01L21/28114 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L27/2481 , H01L29/4236 , H01L29/42376 , H01L29/6656 , H01L29/66621 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1691
摘要： An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.
摘要翻译：集成电路具有包括第一电极，第二电极和离子导电材料的非易失性存储单元。第一和第二电极中的至少一个具有直接接受离子导电材料接受的电化学活性表面。第二电极位于第一电极的正上方。第一电极在第一方向上横向延伸，并且离子导电材料沿与第一方向不同并与第一方向相交的第二方向延伸。仅在第一和第二方向相交的情况下，第一电极直接接收在离子导电材料上。公开了包括方法实施例的其他实施例。

89. 发明授权

US08076717B2 Vertically-oriented semiconductor selection device for cross-point array memory 有权
标题翻译：用于交叉点阵列存储器的垂直取向的半导体选择装置
公开(公告)号：US08076717B2
公开(公告)日：2011-12-13
申请号：US12469433
申请日：2009-05-20
申请人： Gurtej Sandhu , Chandra Mouli , John K. Zahurak
发明人： Gurtej Sandhu , Chandra Mouli , John K. Zahurak
IPC分类号： H01L29/66
CPC分类号： H01L29/7827 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233
摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
摘要翻译：从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。第二掺杂区域电耦合到台面的上表面上的第二硅化物层。栅极导体设置在台面的一个或多个侧壁上。

90. 发明授权

US06593192B2 Method of forming a dual-gated semiconductor-on-insulator device 有权
标题翻译：形成双栅绝缘体上半导体器件的方法
公开(公告)号：US06593192B2
公开(公告)日：2003-07-15
申请号：US09844184
申请日：2001-04-27
申请人： John K. Zahurak , Brent Keeth , Charles H. Dennison
发明人： John K. Zahurak , Brent Keeth , Charles H. Dennison
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

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