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81. 发明申请

US20060151805A1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US20060151805A1
公开(公告)日：2006-07-13
申请号：US11194593
申请日：2005-08-02
申请人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
发明人： Kenji Oota , Yoshihiro Yamaguchi , Hiroshi Yamaguchi
IPC分类号： H01L29/45 , H01L29/76
CPC分类号： H01L29/0661 , H01L29/0619 , H01L29/0834 , H01L29/74
摘要： A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region. With this constitution provided is a power semiconductor device which makes the impurity diffusion length of the anode electrode region shallower in order to ensure reduction in recovery loss.
摘要翻译：功率半导体器件包括半导体衬底，栅电极区域（控制电极区域），阴极电极区域（第一主电极区域），阳极电极区域（第二主电极区域）和保护环。半导体衬底具有侧表面部分，该侧表面部分具有基本上垂直于主表面的垂直部分和在横截面中连接到垂直部分的台面部分。栅电极区域形成在半导体衬底的第一主表面中。阴极电极区域形成在栅电极区域的一部分表面。阳极电极区域形成在半导体衬底的第二主表面中。保护环形成在半导体衬底的第二主表面中并且环形地围绕阳极电极区域。通过这样构成，为了确保降低回收损失，能够使阳极电极区域的杂质扩散长度变浅的功率半导体装置。

82. 发明授权

US06977414B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06977414B2
公开(公告)日：2005-12-20
申请号：US10460407
申请日：2003-06-13
申请人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
发明人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
IPC分类号： H01L21/285 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/28537 , H01L29/0619 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/4238 , H01L29/7801 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域，每个源区域选择性地设置在每个基极区域的表面上。所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极，在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。电场减少区域与栅极电极和源极电极隔离。

83. 发明授权

US06917060B2 Lateral semiconductor device and vertical semiconductor device 失效
标题翻译：侧面半导体器件和垂直半导体器件
公开(公告)号：US06917060B2
公开(公告)日：2005-07-12
申请号：US10662295
申请日：2003-09-16
申请人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
发明人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L29/786 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/74
CPC分类号： H01L29/0696 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A vertical semiconductor device including a first conductivity type base layer having resistance higher then of a first conductivity type buffer layer, the first conductivity type buffer layer formed in one surface portion of the first conductivity type base layer, a second conductivity type drain layer selectively formed in a surface portion of the first conductivity type buffer layer, a second conductivity type base layer selectively formed in the other surface portion of the first conductivity type base layer, a first conductivity type source layer selectively formed in a surface portion of the second conductivity type base layer, a gate insulating film formed on the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer, a gate electrode formed on the second conductivity type base layer via the gate insulating film, a drain electrode electrically connected to the second conductivity type drain layer, and a source electrode electrically connected to the first conductivity type source layer and the second conductivity type base layer, wherein the drain electrode is not electrically connected to the first conductivity buffer layer.
摘要翻译：一种垂直半导体器件，包括具有比第一导电型缓冲层高的电阻的第一导电型基极层，形成在第一导电型基极层的一个表面部分中的第一导电型缓冲层，选择性地形成第二导电型漏极层在第一导电型缓冲层的表面部分中，选择性地形成在第一导电型基底层的另一个表面部分中的第二导电型基极层，选择性地形成在第二导电型基底层的表面部分中的第一导电型源极形成在第一导电型源极层和第一导电型基极层之间的第二导电型基极层上的栅极绝缘膜，经由栅极绝缘膜形成在第二导电型基极层上的栅极电极，漏极电极电连接到第二导电类型漏极层，以及sou rce电极与第一导电型源极层和第二导电型基极层电连接，其中漏极电极不与第一导电性缓冲层电连接。

84. 发明申请

US20050090398A1 Novel tetrazole derivative useful as herbicides 审中-公开
标题翻译：用作除草剂的新型四唑衍生物
公开(公告)号：US20050090398A1
公开(公告)日：2005-04-28
申请号：US10503771
申请日：2003-01-27
申请人： Akihiko Yanagi , Shinichi Narabu , Yoshihiro Yamaguchi , Toshio Goto , Shinichi Shirakura , Chieko Ueno , Shin Nakamura
发明人： Akihiko Yanagi , Shinichi Narabu , Yoshihiro Yamaguchi , Toshio Goto , Shinichi Shirakura , Chieko Ueno , Shin Nakamura
IPC分类号： C07D401/10 , A01N43/713 , A01N43/80 , C07D257/04 , C07D401/12 , C07D403/10 , C07D403/12 , C07D409/10 , C07D409/12 , C07D413/10 , C07D413/12 , C07D417/10 , C07D417/12 , A01N43/647 , C07D257/02
CPC分类号： C07D257/04 , A01N43/713 , C07D403/12
摘要： Compounds of the Formula (I) wherein T represents a group, Q represents a group, R1, R2, R3, R4, R5, R6, R7, T8, R9, R10, R11 are as defined in the description, m represents 0, 1, 2 or 3, n represents 0 or 1, A represents alkylene, processes for preparation, their intermediates and their use in agriculture are described.
摘要翻译：其中T表示基团的式（I）化合物，Q表示基团，R 1，R 2，R 3，R 3， R 4，R 5，R 6，R 7，R 8，R 8， O 9，R 10，R 11，如说明书中所定义，m表示0,1,2或3，n表示0或1， A表示亚烷基，制备方法，其中间体及其在农业中的应用。

85. 发明授权

US06879005B2 High withstand voltage semiconductor device 失效
标题翻译：高耐压半导体器件
公开(公告)号：US06879005B2
公开(公告)日：2005-04-12
申请号：US10790015
申请日：2004-03-02
申请人： Yoshihiro Yamaguchi , Akio Nakagawa
发明人： Yoshihiro Yamaguchi , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/405 , H01L29/0692 , H01L29/0696 , H01L29/404 , H01L29/7811 , H01L29/8611
摘要： A high withstand voltage semiconductor device, comprises: a substrate, a semiconductor layer formed on an upper surface of the substrate, a lateral semiconductor device formed in a surface region of the semiconductor layer and having a first principal electrode in its inner location and a second principal electrode in its outer location so as to let primary current flow between the first and second principal electrodes, a field insulation film formed inside from the second principal electrode in an upper surface of the semiconductor layer to surround the first principal electrode, a resistive field plate formed on an upper surface of the field insulation film to surround the first principal electrode and sectioned in a plurality of circular field plates in an approximate circular arrangement orbiting gradually from the vicinity of the first principal electrode toward the second principal electrode, the innermost one of the circular field plates being electrically connected to the first principal electrode while the outermost one is electrically connected to the second principal electrode, and the resistive field plate including coupling field plates which respectively connect adjacent ones of the circular field plates, and a conductive field plate shaped in a floating state right above spaces defined between pairs of the adjacent circular field plates, an interlayer insulation film being interposed between the conductive field plate and the resistive field plate or the circular field plates, and upon an application of voltage between the first and second principal electrodes, capacities being formed between the conductive field plate and the resistive field plate.
摘要翻译：一种高耐压半导体器件，包括：衬底，形成在衬底的上表面上的半导体层，形成在半导体层的表面区域中并且在其内部具有第一主电极的横向半导体器件，以及第二主电极在其外部位置，以便使第一和第二主电极之间的初级电流流动;在半导体层的上表面内的第二主电极内部形成围绕第一主电极的场绝缘膜，电阻场在所述场绝缘膜的上表面上形成围绕所述第一主电极并且以从所述第一主电极附近朝向所述第二主电极逐渐旋转的大致圆形布置的多个圆形场板分段形成的最内层的圆形场板电连接到第一个主电极，而最外面的电极电连接到第二主电极，并且电阻场板包括分别连接相邻的圆形场板的耦合场板和形成为浮动状态的导电场板，成对的相邻圆形场板，层间绝缘膜插入在导电场板和电阻场板或圆形场板之间，并且在施加第一和第二主电极之间的电压时，容量形成在导电场板和电阻场板。

86. 发明授权

US06650001B2 Lateral semiconductor device and vertical semiconductor device 失效
标题翻译：侧面半导体器件和垂直半导体器件
公开(公告)号：US06650001B2
公开(公告)日：2003-11-18
申请号：US10053657
申请日：2002-01-24
申请人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
发明人： Yoshihiro Yamaguchi , Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L27082
CPC分类号： H01L29/0696 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A lateral semiconductor device includes an n-type buffer layer (15) selectively formed in the surface of an n-type base layer (14), a p-type drain layer (16) selectively formed in the surface of the n-type buffer layer (15), a p-type base layer (17) formed in the surface of the n-type base layer (14) so as to surround the n-type buffer layer (15), an n+-type source layer (18) selectively formed in the surface of the p-type base layer (17), a source electrode (24) in contact with the p-type base layer (17) and the n+-type source layer (18), a drain electrode (22) in contact with the p-type drain layer (16), and a gate electrode (20) formed via a gate insulating film (19) on the surface of the p-type base layer (17) sandwiched between the n+-type source layer (18) and the n-type base layer (14). The p-type drain layer (16) has an annular structure or horseshoe-shaped structure, or is divided into a plurality of portions. This realizes a high breakdown voltage with a low ON voltage.
摘要翻译：横向半导体器件包括：n型缓冲层（15），其选择性地形成在n型基极层（14）的表面; p型漏极层（16），其选择性地形成在n型缓冲层层（15），形成在n型基底层（14）的表面中以围绕n型缓冲层（15）的p型基底层（17），n +型源选择性地形成在p型基底层（17）的表面中的层（18），与p型基底层（17）和n +型源极层（18）接触的源极（24）），与p型漏极层（16）接触的漏电极（22）和在p型基极层（17）的表面上经由栅极绝缘膜（19）形成的栅电极（20）夹在n +型源极层（18）和n型基极层（14）之间。 p型漏极层（16）具有环状结构或马蹄形结构，或分为多个部分。这实现了具有低导通电压的高击穿电压。

87. 发明授权

US06527510B2 Stator blade and stator blade cascade for axial-flow compressor 有权
公开(公告)号：US06527510B2
公开(公告)日：2003-03-04
申请号：US09866924
申请日：2001-05-30
申请人： Markus Olhofer , Bernhard Sendhoff , Edgar Körner , Yoshihiro Yamaguchi , Toyotaka Sonoda , Toshiyuki Arima
发明人： Markus Olhofer , Bernhard Sendhoff , Edgar Körner , Yoshihiro Yamaguchi , Toyotaka Sonoda , Toshiyuki Arima
IPC分类号： F04D2944
CPC分类号： F04D29/681 , F04D21/00 , F04D29/544
摘要： It is an object of the present invention to provide a stator blade for an axial-flow compressor, in which the wave drag due to the generation of a shock wave in a transonic speed range can be suppressed to the minimum. For this purpose, the stator blade in the axial-flow compressor has an intrados producing a positive pressure, and an extrados producing a negative pressure. Both of the intrados and the extrados are located on one side of a chord line. A first bulge and a second bulge are formed on the intrados of the stator blade at a location on the side of a leading edge and on the side of a trailing edge, respectively. Thus, the generation of a shock wave on the extrados can be moderated to reduce the wave drag by positively producing the separation of a boundary layer on the intrados by the first bulge. In addition, the boundary layer rendered unstable by the first bulge on the intrados can be stabilized again by the second bulge on the intrados and hence, the increase in frictional drag due to the separation of the boundary layer on the intrados can be suppressed to the minimum.

88. 外观设计

USD446231S1 Nozzle for a plasma arc torch 失效
公开(公告)号：USD446231S1
公开(公告)日：2001-08-07
申请号：US29128161
申请日：2000-08-21
申请人： Kazuhiro Kuraoka , Yoshihiro Yamaguchi
设计人： Kazuhiro Kuraoka , Yoshihiro Yamaguchi

89. 发明授权

US5994740A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5994740A
公开(公告)日：1999-11-30
申请号：US972148
申请日：1997-11-17
申请人： Akio Nakagawa , Yoshihiro Yamaguchi , Tomoko Matsudai
发明人： Akio Nakagawa , Yoshihiro Yamaguchi , Tomoko Matsudai
IPC分类号： H01L21/84 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/1203
摘要： An n.sup.- -type silicon active layer having a thickness of 6 .mu.m or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the active layer. The two devices are insulated and isolated from each other through a trench. The bipolar transistor has an n-type well layer formed in the surface of the active layer. A p-type well layer is formed in the surface of the n-type well layer. The thickness of the n-type well layer under the p-type well layer is set to be 1 .mu.m or more. A first n.sup.+ -type diffusion layer is formed in the surface of the n-type well layer. A p.sup.+ -type diffusion layer and a second n.sup.+ -type diffusion layer are formed in the surface of the p-type well layer. The n-type well layer and the first n.sup.+ -type diffusion layer serve as a collector region. The p-type well layer and the p.sup.+ -type diffusion layer serve as a base region. The second n.sup.+ -type diffusion layer serves as an emitter region.
摘要翻译：通过氧化硅膜在硅衬底上形成厚度为6μm以下的n型硅有源层。在有源层中形成具有低耐压的npn双极晶体管和具有高耐压的IGBT。两个器件通过沟槽彼此绝缘和隔离。双极晶体管在有源层的表面形成有n型阱层。 p型阱层形成于n型阱层的表面。 p型阱层下面的n型阱层的厚度设定为1μm以上。在n型阱层的表面形成第一n +型扩散层。在p型阱层的表面形成p +型扩散层和第n +型扩散层。 n型阱层和第一n +型扩散层用作集电极区域。 p型阱层和p +型扩散层用作基极区域。第二n +型扩散层用作发射极区域。

90. 发明授权

US5777371A High-breakdown-voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5777371A
公开(公告)日：1998-07-07
申请号：US716863
申请日：1996-09-20
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hideyuki Funaki
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hideyuki Funaki
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/1095 , H01L29/7801 , H01L29/7824 , H01L29/42368
摘要： A high-breakdown-voltage semiconductor device includes a high-resistance semiconductor layer, a drift layer of the first conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a drain layer formed in the surface of the drift layer of the first conductivity type, base layers of the second conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a plurality of island-shaped source layers of the first conductivity type formed in the surfaces of the base layers of the second conductivity type, a gate electrode formed on the base layers of the second conductivity type between the source layers of the first conductivity type and the drift layer of the first conductivity type and between adjacent source layers of the first conductivity type via a gate insulating film, a drain electrode which contacts the drain layer, and source electrodes which contact both the source layers of the first conductivity type and the base layers of the second conductivity type.
摘要翻译：高耐压半导体器件包括高电阻半导体层，选择性地形成在高电阻半导体层的表面中的第一导电类型的漂移层，形成在所述高电阻半导体层的漂移层的表面中的漏极层第一导电类型，选择性地形成在高电阻半导体层的表面中的第二导电类型的基极层，形成在第二导电类型的基极层的表面中的多个第一导电类型的岛状源极层形成在第一导电类型的源极层和第一导电类型的漂移层之间的第二导电类型的基极层上的栅极电极和经由栅极绝缘膜的第一导电类型的相邻源极层之间，与漏极层接触的电极以及接触第一导电类型的源极层的源电极第二导电类型的基层。

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