专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US6132994A Lactosamine oligosaccharides and method for producing the same 有权
标题翻译：乳糖胺寡糖及其制备方法
公开(公告)号：US6132994A
公开(公告)日：2000-10-17
申请号：US230128
申请日：1999-01-22
申请人： Akira Tawada , Keiichi Yoshida
发明人： Akira Tawada , Keiichi Yoshida
IPC分类号： C07H13/06 , C12P19/26
CPC分类号： C12P19/26 , C07H13/06
摘要： A method for producing an N-acetyllactosamine oligosaccharide, comprising the steps of:adjusting a sulfate group content of keratan sulfate;allowing an enzyme having an ability to cleave a glycosidic linkage of keratan sulfate to act on the keratan sulfate with the adjusted sulfate group content to obtain a sulfated N-acetyllactosamine oligosaccharide; andcompletely desulfating said sulfated N-acetyllactosamine oligosaccharide.
摘要翻译： PCT No.PCT / JP97 / 02551 Sec。 371日期1999年1月22日 102（e）日期1999年1月22日PCT提交1997年7月23日PCT公布。第WO98 / 03524号公报日本1998年1月29日制备N-乙酰基乳糖胺寡糖的方法，包括以下步骤：调节硫酸角质素硫酸盐的含量; 允许具有切割硫酸角质素糖苷键的能力的酶作用于具有调整的硫酸根基团含量的硫酸角质素以获得硫酸化N-乙酰乳糖胺寡糖; 并完全脱硫所述硫酸化N-乙酰乳糖胺寡糖。

82. 发明授权

US5699311A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5699311A
公开(公告)日：1997-12-16
申请号：US763667
申请日：1996-12-11
申请人： Hiroshi Sato , Keiichi Yoshida , Tetsuya Tsujikawa
发明人： Hiroshi Sato , Keiichi Yoshida , Tetsuya Tsujikawa
IPC分类号： G11C17/00 , G11C7/00 , G11C7/06 , G11C16/00 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C8/04
CPC分类号： G11C7/00 , G11C16/26 , G11C7/06
摘要： A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.
摘要翻译：一种半导体存储器件，其中包括存储晶体管的多条数据线被包括存储晶体管，按存储数据排列成具有高阈值电压或低阈值电压的矩阵形式，被分成多个块，以及读出放大器用于进行放大时间分散的操作用于放大信号。此外，布置与奇数和偶数编号的相邻数据线相对应的第一组和第二组读出放大器，以便输出一组读出放大器的输出信号，切换字线，另一组感测导致放大器分别执行放大从与这样切换的字线对应的存储单元读出的信号的操作。

83. 发明授权

US5654916A Semiconductor memory device having an improved sense amplifier arrangement 失效
标题翻译：具有改进的读出放大器布置的半导体存储器件
公开(公告)号：US5654916A
公开(公告)日：1997-08-05
申请号：US510465
申请日：1995-08-02
申请人： Hiroshi Sato , Keiichi Yoshida , Tetsuya Tsujikawa
发明人： Hiroshi Sato , Keiichi Yoshida , Tetsuya Tsujikawa
IPC分类号： G11C17/00 , G11C7/00 , G11C7/06 , G11C16/00 , G11C16/06 , G11C16/26 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C7/00 , G11C16/26 , G11C7/06
摘要： A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.
摘要翻译：一种半导体存储器件，其中包括存储晶体管的多条数据线被包括存储晶体管，按存储数据排列成具有高阈值电压或低阈值电压的矩阵形式，被分成多个块，以及读出放大器用于进行放大时间分散的操作用于放大信号。此外，布置与奇数和偶数编号的相邻数据线相对应的第一组和第二组读出放大器，以便输出一组读出放大器的输出信号，切换字线，另一组感测导致放大器分别执行放大从与这样切换的字线对应的存储单元读出的信号的操作。

84. 发明授权

US5532971A Nonvolatile semiconductor memory having enhanced speed for erasing and programming 失效
标题翻译：具有提高擦除和编程速度的非易失性半导体存储器
公开(公告)号：US5532971A
公开(公告)日：1996-07-02
申请号：US354639
申请日：1994-12-13
申请人： Toshihiro Tanaka , Masataka Kato , Keiichi Yoshida , Hitoshi Kume , Yoshinobu Nakagome , Katsutaka Kimura
发明人： Toshihiro Tanaka , Masataka Kato , Keiichi Yoshida , Hitoshi Kume , Yoshinobu Nakagome , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/12 , G11C8/00 , G11C11/34
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.
摘要翻译：提供了一种布置，以提高由单个电源电压驱动的非易失性半导体存储器的擦除和编程操作的速度，并且减少构成子字解码器电路的晶体管的数量，从而使器件的尺寸最小化。为此，在驱动字线Wi1-Wij的子字解码器电路WDi1-WDij中，将从第一地址线组产生的块选择地址线Bip和Bin用作控制电压的逆变器电路的电源电压字线和从第二地址线组产生的选通选择地址线Gj用于栅极输入线。

85. 发明授权

US5221179A Vacuum pump 失效
标题翻译：真空泵
公开(公告)号：US5221179A
公开(公告)日：1993-06-22
申请号：US769409
申请日：1991-10-01
申请人： Tatsuji Ikegami , Tetsuro Ohbayashi , Keiichi Yoshida , Masashi Iguchi
发明人： Tatsuji Ikegami , Tetsuro Ohbayashi , Keiichi Yoshida , Masashi Iguchi
IPC分类号： F04D19/04
CPC分类号： F04D19/04
摘要： Disclosed is a vacuum pump having a peripheral groove vacuum pump unit which includes a casing provided with an inlet port and an outlet port; a rotor disposed within the casing and including a rotor shaft journaled on the casing, a rotor body fixed to the rotor shaft and provided integrally with a rotor disk; and a stator fixedly disposed within the casing and provided with an annular groove receiving the peripheral portion of the rotor disk. Both sides of the peripheral portion of the rotor disk are cut in steps or portions of the side walls of the annular groove corresponding to the peripheral portion of the rotor disk are cut in annular recesses to form flow passages on both sides of the peripheral portion of the rotor disk. Partitions are projected from the stator into the flow passages. The starting ends of the flow passages on the inlet side of the partitions communicate with the inlet port, and the terminating ends of the same on the outlet side of the partitions communicate with the outlet port. The vacuum pump is capable of operating at a high pumping speed. Spaces between the peripheral portion of the rotor disk and the inner surfaces of the annular groove of the stator need not be sealed and large clearances may be formed therebetween, so that the components of the vacuum pump can easily be machined without requiring high machining accuracies.
摘要翻译：公开了一种真空泵，其具有周边槽真空泵单元，其包括设置有入口端口和出口的壳体; 转子，其设置在所述壳体内并且包括在所述壳体上轴颈的转子轴，固定到所述转子轴并与转子盘一体设置的转子体; 以及定子，其固定地设置在所述壳体内并且设置有容纳所述转子盘的周边部的环状槽。转子盘的外围部分的两侧被切割成台阶，或者与转子盘的周边部分相对应的环形槽的侧壁的一部分被切割成环形凹槽，以在周向部分的外围部分的两侧形成流动通道转子盘。定子从定子突出到流动通道中。隔板入口侧的流动通道的起始端与入口连通，其间隔出口侧的端部与出口相通。真空泵能够以高泵送速度运行。转子盘的周边部分和定子的环形槽的内表面之间的间隙不需要被密封，并且可以在它们之间形成大的间隙，从而可以容易地加工真空泵的部件，而不需要高的加工精度。

86. 发明申请

US20170090342A1 DEVELOPING DEVICE AND IMAGE FORMING APPARATUS AND PROCESS CARTRIDGE INCORPORATING SAME 有权
公开(公告)号：US20170090342A1
公开(公告)日：2017-03-30
申请号：US15282172
申请日：2016-09-30
申请人： Tatsuya OHHIRA , Atsushi Kurokawa , Masayuki Yamane , Keiichi Yoshida , Toshiki Hayashi
发明人： Tatsuya OHHIRA , Atsushi Kurokawa , Masayuki Yamane , Keiichi Yoshida , Toshiki Hayashi , Shunji Katoh
IPC分类号： G03G15/08 , G03G15/09
CPC分类号： G03G15/0812 , G03G15/09 , G03G15/0921 , G03G2215/0132 , G03G2215/0838
摘要： A developing device includes a developer bearer, a magnetic field generator, a easing having an opening, a developer conveyor to rotate inside a developer containing compartment below the developer bearer, and a developer regulator. A side wall of the casing defines a bottom end of the opening, and the developer regulator is disposed on the side wall. The side wall includes an upper end face facing the developer bearer below an axis of the developer bearer and a curved inner face along an orbit of rotation of the developer conveyor, extending from below the developer conveyor toward the upper end face. On a virtual plane perpendicular to the axis of the developer bearer, an intersection between a tangent line to an upper end of the curved inner face and the surface of the developer bearer is in a range from a tangential magnetic-flux peak and a closest approach point.

87. 发明授权

US07826786B2 Image forming apparatus, lubricant applying device, transfer device, process cartridge, and toner 有权
标题翻译：图像形成装置，润滑剂涂布装置，转印装置，处理盒和调色剂
公开(公告)号：US07826786B2
公开(公告)日：2010-11-02
申请号：US10588957
申请日：2005-12-06
申请人： Takeo Suda , Shinichi Kawahara , Takatsugu Fujishiro , Tokuya Ojimi , Takeshi Tabuchi , Masato Yanagida , Haruji Mizuishi , Teruyuki Kasuga , Hiroomi Harada , Shuji Tanaka , Takaaki Tawada , Hiroshi Ono , Ken Amemiya , Toshio Koike , Yuji Arai , Masanori Kawasumi , Takuzi Yoneda , Masami Tomita , Yutaka Takahashi , Yoshio Hattori , Keiichi Yoshida
发明人： Takeo Suda , Shinichi Kawahara , Takatsugu Fujishiro , Tokuya Ojimi , Takeshi Tabuchi , Masato Yanagida , Haruji Mizuishi , Teruyuki Kasuga , Hiroomi Harada , Shuji Tanaka , Takaaki Tawada , Hiroshi Ono , Ken Amemiya , Toshio Koike , Yuji Arai , Masanori Kawasumi , Takuzi Yoneda , Masami Tomita , Yutaka Takahashi , Yoshio Hattori , Keiichi Yoshida
IPC分类号： G03G21/00
CPC分类号： G03G21/0011
摘要： In an image forming apparatus, an area applied with a lubricant, i.e., an area of a lubricant layer having a uniform thickness, is obtained by spreading the lubricant by a lubricant smoothing blade. The area applied with a lubricant covers an area cleaned by a cleaning blade, i.e., a contact portion of the cleaning blade with a photoconductor.
摘要翻译：在图像形成装置中，通过润滑剂平滑刮刀涂布润滑剂，获得涂有润滑剂的区域，即具有均匀厚度的润滑剂层的区域。涂有润滑剂的区域覆盖由清洁刮板清洁的区域，即清洁刮板与感光体的接触部分。

88. 发明授权

US07463852B2 Image forming apparatus having a developer conveying system and associated methodology 有权
标题翻译：具有显影剂输送系统和相关方法的图像形成装置
公开(公告)号：US07463852B2
公开(公告)日：2008-12-09
申请号：US11543830
申请日：2006-10-06
申请人： Keiichi Yoshida , Yoshio Hattori , Shinichi Kawahara , Takatsugu Fujishiro , Shuji Tanaka
发明人： Keiichi Yoshida , Yoshio Hattori , Shinichi Kawahara , Takatsugu Fujishiro , Shuji Tanaka
IPC分类号： G03G15/08
CPC分类号： G03G15/0822 , G03G2215/0822 , G03G2215/0827
摘要： An image forming apparatus includes an image carrier configured to form a latent image and a development unit including a development member configured to develop the latent image forming on the image carrier with a developer, and a plurality of conveying members each including at least one spiral vane and configured to rotate around a spiral axis of the spiral vane to revolve and transfer the developer around the spiral axis in a direction along the spiral axis, the plurality of conveying members configured to transfer the developer sequentially from a conveying member to an adjacent conveying member and including a first conveying member arranged at a position closest to the development member to supply developer to the development member, wherein a number of the spiral vanes of the first conveying member are at least two and is also greater than the number of spiral vanes in the remaining conveying members.
摘要翻译：图像形成装置包括被构造成形成潜像的图像载体和显影单元，显影单元包括显影部件，显影部件被构造成用显影剂显影在图像载体上形成的潜像，以及多个输送部件，每个输送部件包括至少一个螺旋叶片并且构造成围绕所述螺旋叶片的螺旋轴线旋转，以沿着所述螺旋轴线的方向围绕所述螺旋轴线旋转和传送所述显影剂，所述多个输送构件被构造成将所述显影剂从输送构件依次传送到相邻的输送构件并且包括布置在最靠近显影构件的位置处以将显影剂供应到显影构件的第一输送构件，其中第一输送构件的多个螺旋叶片为至少两个并且还大于螺旋叶片的数量剩余的输送构件。

89. 发明授权

US07334080B2 Nonvolatile memory with independent access capability to associated buffer 有权
标题翻译：非易失性存储器，具有对相关缓冲区的独立访问能力
公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

90. 发明授权

US07290109B2 Memory system and memory card 有权
标题翻译：内存系统和存储卡
公开(公告)号：US07290109B2
公开(公告)日：2007-10-30
申请号：US10500252
申请日：2002-01-09
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.
摘要翻译：存储器系统包括多个非易失性存储器芯片（CHP 1和CHP 2），每个非易失性存储器芯片具有可独立于彼此执行存储器操作的多个存储器组（BNK 1和BNK 2）和存储器控制器（5）控制以访问每个所述非易失性存储器芯片。存储器控制器可以选择性地指示在非易失性存储器芯片的多个存储体上的同时写入操作或交错写入操作。因此，在同时写入操作中，可以完全并行地执行比写入建立时间长得多的写入操作。在交错写入操作中，可以执行写入设置之后的写入操作，以便部分地与另一个存储体上的写入操作重叠。结果，可以使构成高速写入操作的存储器系统的非易失性存储器芯片的数量相对较小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式