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81. 发明授权

US5537577A Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions 失效
标题翻译：交错存储器，其中包括多个存储体的多个存储器装置同时输出数据，同时控制单元以上升和下降方向排列地址
公开(公告)号：US5537577A
公开(公告)日：1996-07-16
申请号：US58530
申请日：1993-05-06
申请人： Toshio Sugimura , Katsuhiko Ueda , Minoru Okamoto , Toshihiro Ishikawa , Mikako Yasutome
发明人： Toshio Sugimura , Katsuhiko Ueda , Minoru Okamoto , Toshihiro Ishikawa , Mikako Yasutome
IPC分类号： F02B75/02 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0607 , F02B2075/025
摘要： An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.
摘要翻译：一种交织存储器系统，具有第一存储器装置，该第一存储器装置包括一个0组和一个一组，用于同时从该第一存储区输出来自0组的偶数地址的数据和奇数地址的数据;第二存储器装置包括0行和1行，用于从0行同时从偶数行地址输出数据和来自1行的奇数地址的数据;以及保持装置，用于从一个存储体中的一个存储区中保存数据第一存储器件和第二存储器件之一，用于将数据的输出延迟1/2个周期时间用于顺序寻址。控制器控制第一和第二选择装置，其中当从第一或第二存储装置中的偶数地址以连续地址的升序输出数据时，交替地选择0组和1组，或者在来自第一或第二存储器件中的奇数地址的连续地址的降序。此外，当从第一存储装置中的偶数地址以连续地址的降序输出数据时，交替地选择第一保持装置和输出未被第一保持装置保持的存储体，或者以升序来自第一存储设备中的奇数地址的连续地址的顺序。类似地，第二保持装置和输出没有被第二保持装置保持的组。

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