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81. 发明授权

US08456006B2 Hybrid interconnect structure for performance improvement and reliability enhancement 有权
标题翻译：混合互连结构，用于性能改进和可靠性提升
公开(公告)号：US08456006B2
公开(公告)日：2013-06-04
申请号：US13174841
申请日：2011-07-01
申请人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
发明人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76841 , H01L21/7682 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要翻译：本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地，气隙。与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

82. 发明申请

US20130112462A1 Metal Alloy Cap Integration 审中-公开
标题翻译：金属合金盖整合
公开(公告)号：US20130112462A1
公开(公告)日：2013-05-09
申请号：US13290557
申请日：2011-11-07
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H05K1/09 , H05K3/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76849 , H01L21/76877 , H01L21/76882 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要翻译：包括金属合金覆盖层的金属互连结构及其制造方法。互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。因此，互连结构中的残余合金元素的电阻率冲击降低。也就是说，在金属互连结构的特征内部存在合金元素的减少。金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。

83. 发明授权

US08404582B2 Structure and method for manufacturing interconnect structures having self-aligned dielectric caps 有权
标题翻译：用于制造具有自对准电介质盖的互连结构的结构和方法
公开(公告)号：US08404582B2
公开(公告)日：2013-03-26
申请号：US12773306
申请日：2010-05-04
申请人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
摘要翻译：提供具有自对准电介质盖的互连结构。在基板上形成至少一个金属化层。电介质盖被选择性地沉积在金属化层上。

84. 发明申请

US20130069161A1 INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP 有权
标题翻译：具有选择性金属盖的集成电路结构
公开(公告)号：US20130069161A1
公开(公告)日：2013-03-21
申请号：US13233064
申请日：2011-09-15
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L29/42372 , H01L21/28247 , H01L21/76834 , H01L21/7685 , H01L21/76856 , H01L21/76888 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/78
摘要： Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.
摘要翻译：在栅极上利用选择性地形成和至少部分氧化的金属盖形成集成电路结构的方法以及相关联的结构。在一个实施例中，一种方法包括提供包括具有金属栅极的晶体管的前体结构; 在所述金属栅极的暴露部分上形成蚀刻停止层; 至少部分氧化所述蚀刻停止层; 以及在所述至少部分氧化的蚀刻停止层上形成电介质层。

85. 发明申请

US20130065376A1 SEMICONDUCTOR CAPACITOR 失效
标题翻译：半导体电容器
公开(公告)号：US20130065376A1
公开(公告)日：2013-03-14
申请号：US13616882
申请日：2012-09-14
申请人： David Vaclav Horak , Shom Ponoth , Hosadurga Shobha , Chih-Chao Yang
发明人： David Vaclav Horak , Shom Ponoth , Hosadurga Shobha , Chih-Chao Yang
IPC分类号： H01L21/02
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.
摘要翻译：公开了一种半导体电容器及其制造方法。使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。

86. 发明申请

US20130001789A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20130001789A1
公开(公告)日：2013-01-03
申请号：US13617060
申请日：2012-09-14
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

87. 发明申请

US20120329270A1 SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS 有权
标题翻译：表面修复结构和互连应用程序
公开(公告)号：US20120329270A1
公开(公告)日：2012-12-27
申请号：US13603051
申请日：2012-09-04
申请人： Chih-Chao Yang , Conal E. Murray
发明人： Chih-Chao Yang , Conal E. Murray
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , Y02P80/30 , H01L2924/00
摘要： A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material.
摘要翻译：提供了一种方法，其包括提供具有约4.0或更小的介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与电介质材料的上表面共面的上表面，所述至少一个导电材料的上表面具有向内延伸到所述至少一个导电材料中的中空金属相关缺陷; 并用表面修复材料填充与中空金属相关的缺陷。

88. 发明申请

US20120326237A1 LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME 有权
标题翻译：低剖面局部互连及其制作方法
公开(公告)号：US20120326237A1
公开(公告)日：2012-12-27
申请号：US13169081
申请日：2011-06-27
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L29/772
CPC分类号： H01L21/76895 , H01L21/823475 , H04L45/58 , H04L49/15 , H04L49/45
摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
摘要翻译：本发明的实施例提供一种结构。该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触点晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。

89. 发明申请

US20120306048A1 ELECTRICALLY PROGRAMMABLE METAL FUSE 有权
标题翻译：电气可编程金属保险丝
公开(公告)号：US20120306048A1
公开(公告)日：2012-12-06
申请号：US13149108
申请日：2011-05-31
申请人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
发明人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5256 , G11C17/16 , G11C29/785 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
摘要翻译：金属电可编程保险丝（eFuse）包括在金属条的两端处具有与宽金属线部分相邻的金属线的具有宽度大于金属带宽度的宽度的金属带。条带宽度可以是光刻最小尺寸，并且金属条带的长度与条带宽度的比率大于5以在编程期间定位围绕金属条的中心的加热。加热的本地化减少了用于编程金属eFuse所需的电力。此外，在金属带的长于Blech长度的部分内的编程期间形成逐渐的温度梯度，使得金属的电迁移在金属带的中心部分逐渐发生。金属线部分提供与金属eFuse相同的水平，以物理阻挡编程期间产生的碎屑。

90. 发明授权

US08304912B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US08304912B2
公开(公告)日：2012-11-06
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

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