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81. 发明授权

US06803982B2 In-plane switching mode liquid crystal display device including common electrode on passivation layer which is formed over TFT and data electrode 有权
标题翻译：面内切换模式液晶显示装置，包括形成在TFT和数据电极上的钝化层上的公共电极
公开(公告)号：US06803982B2
公开(公告)日：2004-10-12
申请号：US10015765
申请日：2001-12-17
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： G02F11343
CPC分类号： G02F1/134363 , G02F1/136213
摘要： An in-plane switching mode liquid crystal display device is disclosed which comprises first and second substrates, a plurality of gate and data bus lines formed on said first substrate to define a plurality of pixel regions, a common bus line aligned in each pixel regions of the first substrate, a thin film transistor (TFT) formed at each pixel regions of the first substrate, a data electrode which is formed on a gate insulator of the TFT and has a portion overlapping the common bus line for forming a first storage capacitor, a passivation layer formed over the data electrode and the TFT, a common electrode which is formed on the passivation layer so as to overlap the gate and data bus lines and has a portion overlapping said data electrode for forming a second storage capacitor, and a liquid crystal layer formed between the first and second substrates.
摘要翻译：公开了一种面内切换模式液晶显示装置，其包括第一和第二基板，形成在所述第一基板上以限定多个像素区域的多个栅极和数据总线线，在每个像素区域中对齐的公共总线所述第一基板，形成在所述第一基板的每个像素区域处的薄膜晶体管（TFT），形成在所述TFT的栅绝缘体上并且具有与所述公共总线重叠的部分以形成第一存储电容器的数据电极，在数据电极和TFT上形成的钝化层，形成在钝化层上以与栅极和数据总线重叠并具有与用于形成第二存储电容器的数据电极重叠的部分的公共电极，以及液体形成在第一和第二基板之间的晶体层。

82. 发明授权

US06514614B1 Coated nucleus for a cultured pearl 失效
标题翻译：用于培养珍珠的包被核
公开(公告)号：US06514614B1
公开(公告)日：2003-02-04
申请号：US09572370
申请日：2000-05-18
申请人： Hiroshi Komatsu , Hiroshi Ito
发明人： Hiroshi Komatsu , Hiroshi Ito
IPC分类号： B32B516
CPC分类号： A01K61/54 , Y02A40/822 , Y10T428/2982 , Y10T428/2991 , Y10T428/2993 , Y10T428/2998
摘要： The present invention is a coated nucleus for a cultured pearl whose surface is coated with water soluble polymer, characterizing over 25% of total coated amount of said water soluble polymer is dissolved by soaking said coated nucleus into seawater of 15° C. temperature for 30 minutes.
摘要翻译：本发明是一种用于培养珍珠的涂层核，其表面涂覆有水溶性聚合物，其特征在于所述水溶性聚合物的总涂布量的25％以上通过将所述涂覆的核浸入15℃的海水中而溶解30 分钟。

83. 发明授权

US06400436B1 In-plane switching mode liquid crystal display device with specific arrangement of common bus line, data electrode and common electrode 有权
标题翻译：平面开关模式液晶显示装置具有公共总线，数据电极和公共电极的特定布置
公开(公告)号：US06400436B1
公开(公告)日：2002-06-04
申请号：US09613730
申请日：2000-07-11
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： G02F11343
CPC分类号： G02F1/134363 , G02F1/136213
摘要： An in-plane switching mode liquid crystal display device. The device comprises first and second substrates, a plurality of gate and data bus lines formed on the first substrate to define a plurality of pixel regions, a common bus line aligned in each pixel regions of the first substrate, a thin film transistor (TFT) formed at each pixel regions of the first substrate, a data electrode which is formed on a gate insulator of the TFT and has a portion overlying the common bus line for forming a first storage capacitor, a passivation layer formed over the data electrode and the TFT, a common electrode which is formed on the passivation layer so as to overlap the gate and data bus lines and has a portion overlying the data electrode for forming a second storage capacitor, and a liquid crystal layer formed between the first and second substrates.
摘要翻译：一种面内切换模式液晶显示装置。该器件包括第一和第二衬底，形成在第一衬底上以限定多个像素区域的多个栅极和数据总线线，在第一衬底的每个像素区域中对准的公共总线线，薄膜晶体管（TFT）形成在所述第一基板的每个像素区域处的数据电极，形成在所述TFT的栅极绝缘体上并且具有覆盖所述公共总线的部分以形成第一存储电容器的数据电极，形成在所述数据电极和所述TFT上的钝化层形成在钝化层上以与栅极和数据总线重叠并且具有覆盖数据电极以形成第二存储电容器的部分的共用电极以及形成在第一和第二基板之间的液晶层。

84. 外观设计

USD456021S1 Electronic image data input/output apparatus 失效
标题翻译：电子图像数据输入/输出装置
公开(公告)号：USD456021S1
公开(公告)日：2002-04-23
申请号：US29137945
申请日：2001-03-05
申请人： Hiroshi Komatsu
设计人： Hiroshi Komatsu

85. 发明授权

US06335770B1 In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode 失效
标题翻译：平面切换模式LCD，具有公共总线，数据电极和公共电极的特定布置
公开(公告)号：US06335770B1
公开(公告)日：2002-01-01
申请号：US09116707
申请日：1998-07-17
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： G02F11343
CPC分类号： G02F1/134363 , G02F1/136213
摘要： An in-plane switching mode liquid crystal display device. The device coprises first and second substrates, a plurality of gate and data bus lines formed on the first substrate to define a plurality of pixel regions, a common bus line aligned in each pixel regions of the first substrate, a thin film transistor (TFT) formed at each pixel regions of the first substrate, a data electrode which is formed on a gate insulator of the TFT and has a portion overlying the common bus line for forming a first storage capacitor, a passivation layer formed over the data electrode and the TFT, a common electrode which is formed on the passivation layer so as to overlap the gate and data bus lines and has a portion overlying the data electrode for forming a second storage capacitor, and a liquid crystal layer formed between the first and second substrates.
摘要翻译：一种面内切换模式液晶显示装置。所述装置共同构成第一和第二基板，形成在第一基板上以限定多个像素区域的多个栅极和数据总线线，在第一基板的每个像素区域中排列的公共总线线，薄膜晶体管（TFT）形成在所述第一基板的每个像素区域处的数据电极，形成在所述TFT的栅极绝缘体上并且具有覆盖所述公共总线的部分以形成第一存储电容器的数据电极，形成在所述数据电极和所述TFT上的钝化层形成在钝化层上以与栅极和数据总线重叠并且具有覆盖数据电极以形成第二存储电容器的部分的共用电极以及形成在第一和第二基板之间的液晶层。

86. 发明授权

US06218274B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06218274B1
公开(公告)日：2001-04-17
申请号：US09178892
申请日：1998-10-27
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28035 , H01L21/82345
摘要： A gate oxide film is formed on a silicon substrate, and a gate electrode is formed on the gate oxide film. The gate electrode is a polysilicon film that is given p+ conductivity because of doping with B. An Si3N4 film is formed on the top surface of the gate electrode and sidewall spacers of Si3N4 are formed on the side walls of the gate electrode. An interlayer insulating film of SiO2 is formed on the Si3N4 film, the sidewall spacers, and a LOCOS oxide film. This structure inhibits diffusion of B from the gate electrode to the interlayer insulating film in a heating process that is executed after the formation of the gate electrode.
摘要翻译：在硅衬底上形成栅极氧化膜，在栅氧化膜上形成栅电极。栅电极是由于掺杂B而被赋予p +导电性的多晶硅膜。在栅电极的顶表面上形成Si 3 N 4膜，并且在栅电极的侧壁上形成Si 3 N 4的侧壁间隔物。在Si 3 N 4膜，侧壁间隔物和LOCOS氧化物膜上形成SiO 2的层间绝缘膜。这种结构在形成栅电极之后执行的加热过程中抑制B从栅电极到层间绝缘膜的扩散。

87. 发明授权

US06214693B1 Process for the production of semiconductor device 失效
标题翻译：半导体器件生产工艺
公开(公告)号：US06214693B1
公开(公告)日：2001-04-10
申请号：US09404801
申请日：1999-09-24
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L2176
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L29/78648
摘要： A process for the production of a semiconductor device comprising the steps of; (a) forming a patterned mask layer on a surface of a semiconductor substrate, (b) etching the semiconductor substrate using the mask layer as an etching mask, to form a step between a portion of the semiconductor substrate covered with the mask layer and an etched portion of the semiconductor substrate, (c) forming an insulating film on the entire surface, and then planarizing the insulating film to cover the etched portion of the semiconductor substrate with the insulating film, (d) removing the mask layer, then, forming a first gate insulating film on an exposed surface of the semiconductor substrate, then forming a first gate electrode on the first gate insulating film, and at the same time, forming a first word line extending from the first gate electrode on the insulating film, (e) forming an interlayer on the entire surface, and bonding the semiconductor substrate and a supporting substrate to each other through the interlayer, (f) grinding and polishing the semiconductor substrate from its rear surface to expose a bottom surface of the insulating film and to leave a semiconductive layer which is the semiconductor substrate remaining after the polishing, surrounded by the insulating film, and (g) forming a second gate insulating film on an exposed surface of the semiconductive layer, then forming a second gate electrode on the second gate insulating film, and at the same time, forming a second word line extending from the second gate electrode on the insulating film.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的表面上形成图案化的掩模层，（b）使用掩模层作为蚀刻掩模蚀刻半导体衬底，以在被掩模层覆盖的半导体衬底的一部分和蚀刻部分，（c）在整个表面上形成绝缘膜，然后用绝缘膜平面化绝缘膜以覆盖半导体衬底的蚀刻部分，（d）去除掩模层，然后形成在所述半导体衬底的暴露表面上的第一栅极绝缘膜，然后在所述第一栅极绝缘膜上形成第一栅电极，并且同时形成从所述绝缘膜上的所述第一栅电极延伸的第一字线（ e）在整个表面上形成中间层，并通过中间层将半导体衬底和支撑衬底彼此接合，（f）研磨和抛光半导体衬底从其后表面露出绝缘膜的底表面，并且留下半导体层，半导体衬底是抛光之后残留的半导体衬底，被绝缘膜包围，并且（g）在暴露表面上形成第二栅极绝缘膜然后在第二栅极绝缘膜上形成第二栅电极，同时形成从绝缘膜上的第二栅电极延伸的第二字线。

88. 外观设计

USD421044S Sorter/book-binder of copying machine 失效
公开(公告)号：USD421044S
公开(公告)日：2000-02-22
申请号：US87823
申请日：1998-05-11
申请人： Hiroshi Komatsu
设计人： Hiroshi Komatsu

89. 发明授权

US5719083A Method of forming a complex film over a substrate having a specifically selected work function 失效
标题翻译：在具有特定工作功能的基板上形成复合膜的方法
公开(公告)号：US5719083A
公开(公告)日：1998-02-17
申请号：US480894
申请日：1995-06-07
申请人： Hiroshi Komatsu
发明人： Hiroshi Komatsu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/45 , H01L29/49 , H01L21/8232 , H01L21/44
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28518 , H01L21/28525 , H01L21/76843 , H01L21/76855 , H01L21/76859 , H01L21/76864 , H01L23/485 , H01L23/53223 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4975 , H01L29/6659 , H01L2924/0002
摘要： Disclosed is a method and an apparatus for making devices with low barrier height. In fabricating an n-channel and p-channel devices, hemisphere grains, silicon crystal grains and metal silicide crystal grains are formed on a contact-hole or a gate electrode on an insulating film in each semiconductor element, so that it becomes possible to control the work function, to reduce the contact resistance, and to control the threshold voltage V.sub.th.
摘要翻译：公开了一种用于制造屏障高度低的装置的方法和装置。在制造n沟道和p沟道器件时，在每个半导体元件中的绝缘膜上的接触孔或栅电极上形成半球晶粒，硅晶粒和金属硅化物晶粒，使得可以控制工作功能，降低接触电阻，并控制阈值电压Vth。

90. 发明授权

US5453316A Composite electronic part 失效
标题翻译：复合电子部件
公开(公告)号：US5453316A
公开(公告)日：1995-09-26
申请号：US240327
申请日：1994-05-10
申请人： Hiroshi Morii , Hiroshi Komatsu , Tomoaki Ushiro , Tomio Yamasaki , Toshio Kawabata
发明人： Hiroshi Morii , Hiroshi Komatsu , Tomoaki Ushiro , Tomio Yamasaki , Toshio Kawabata
IPC分类号： H01G4/12 , H01G4/40 , H03H3/00 , H03H7/01 , B32B9/00
CPC分类号： H03H3/00 , H01G4/40 , H03H7/0115 , H03H2001/0057 , H03H2001/0085 , Y10S428/901 , Y10T428/24926 , Y10T428/31678
摘要： A composite electronic part includes a dielectric ceramic portion consisting of a Pb group dielectric material. Inside the dielectric ceramic portion, an internal electrode constituting a portion of a capacitor is formed. The dielectric ceramic portion is bonded to a magnetic ceramic portion consisting of a Ni--Zn group ferrite material by an intermediate layer consisting of a ceramic material containing Pb, Ni, Fe and Nb as main components. Inside the magnetic ceramic portion, an internal electrode constituting a portion of an inductor is formed. Furthermore, at end portions of the dielectric ceramic portion, intermediate layer and magnetic ceramic portion, a plurality of external electrodes consisting of, for example, Ag are formed, and connected to the predetermined internal electrodes.
摘要翻译：复合电子部件包括由Pb族电介质材料构成的电介质陶瓷部。在介质陶瓷部分内部，形成构成电容器的一部分的内部电极。介电陶瓷部通过由含有Pb，Ni，Fe和Nb作为主要成分的陶瓷材料构成的中间层与Ni-Zn系铁氧体材料组成的磁性陶瓷部分接合。在磁陶瓷部分内形成构成电感器的一部分的内部电极。此外，在介质陶瓷部分，中间层和磁性陶瓷部分的端部，形成由例如Ag组成的多个外部电极，并连接到预定的内部电极。

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