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81. 发明申请

US20080316832A1 NON-VOLATILE STORAGE SYSTEM WITH INTELLIGENT CONTROL OF PROGRAM PULSE DURATION 有权
标题翻译：具有智能控制程序脉冲持续时间的非易失性存储系统
公开(公告)号：US20080316832A1
公开(公告)日：2008-12-25
申请号：US11766580
申请日：2007-06-21
申请人： Yupin Fong , Jun Wan
发明人： Yupin Fong , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C16/349
摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.
摘要翻译：为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。在一个实施例中，例如，在脉冲达到最大幅度之后，脉冲宽度增加。在另一个实施例中，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

82. 发明授权

US07457178B2 Trimming of analog voltages in flash memory devices 有权
标题翻译：微调闪存设备中的模拟电压
公开(公告)号：US07457178B2
公开(公告)日：2008-11-25
申请号：US11331479
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C16/30 , G11C11/5628 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

83. 发明授权

US07454319B2 System, method, and computer program product for determining wall thickness in graphic model 失效
标题翻译：用于确定图形模型中壁厚的系统，方法和计算机程序产品
公开(公告)号：US07454319B2
公开(公告)日：2008-11-18
申请号：US10717273
申请日：2003-11-19
申请人： Jun Wan , Chee-Keong Chong , Zhi Li
发明人： Jun Wan , Chee-Keong Chong , Zhi Li
IPC分类号： G06K9/36
CPC分类号： G06T17/20 , G06F17/5018
摘要： A system, method, and computer program product for measuring wall thickness. After an internal body topology of the model is generated, the topology is traversed between wall elements to determine wall thickness.
摘要翻译：一种用于测量壁厚的系统，方法和计算机程序产品。在生成模型的内部结构拓扑之后，在壁元素之间遍历拓扑以确定壁厚。

84. 发明授权

US07447086B2 Selective program voltage ramp rates in non-volatile memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US07447086B2
公开(公告)日：2008-11-04
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

85. 发明申请

US20080158990A1 RETENTION MARGIN PROGRAM VERIFICATION 有权
标题翻译：保留MARGIN程序验证
公开(公告)号：US20080158990A1
公开(公告)日：2008-07-03
申请号：US11617546
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

86. 发明申请

US20080158989A1 RETENTION MARGIN PROGRAM VERIFICATION 有权
标题翻译：保留MARGIN程序验证
公开(公告)号：US20080158989A1
公开(公告)日：2008-07-03
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译：提供了使用部分数据保留余量的存储器件中的数据验证。从区域读取位计数，以确定错误是否会导致内存。在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

87. 发明授权

US07349258B2 Reducing read disturb for non-volatile storage 有权
公开(公告)号：US07349258B2
公开(公告)日：2008-03-25
申请号：US11295776
申请日：2005-12-06
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

88. 发明申请

US20070159888A1 FLASH MEMORY DEVICES WITH TRIMMED ANALOG VOLTAGES 有权
标题翻译：具有TRIMMED模拟电压的闪存存储器件
公开(公告)号：US20070159888A1
公开(公告)日：2007-07-12
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

89. 发明申请

US20070153573A1 SYSTEM FOR REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 有权
标题翻译：减少阅读障碍的非挥发性储存系统
公开(公告)号：US20070153573A1
公开(公告)日：2007-07-05
申请号：US11681188
申请日：2007-03-02
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

90. 发明授权

US07075360B1 Super-PTAT current source 有权
标题翻译：超级PTAT电流源
公开(公告)号：US07075360B1
公开(公告)日：2006-07-11
申请号：US10954698
申请日：2004-09-29
申请人： Peter R. Holloway , Jun Wan
发明人： Peter R. Holloway , Jun Wan
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A super-PTAT current source receives a PTAT reference voltage as input. The PTAT reference voltage is combined with the gate-to-source voltage difference of two unequal-area input transistors and the combined voltage is imposed on a high negative temperature coefficient resistor to produce an output current that is super-PTAT. A current source supplies a bias current to the super-PTAT current source whereby excess current provided by the current source is consumed by closed loop adjustments. The super-PTAT current source generates a super-PTAT current having a constant slope, excellent stability and very good linearity. In one embodiment, the super-PTAT output current is mixed with a sub-PTAT current in a preselected ratio to generate output currents having exactly the desired temperature coefficient.
摘要翻译：超级PTAT电流源接收PTAT参考电压作为输入。 PTAT参考电压与两个不等面积输入晶体管的栅极 - 源极电压差相结合，组合电压施加在高负温度系数电阻上，产生超级PTAT的输出电流。电流源向超级PTAT电流源提供偏置电流，由此由电流源提供的过电流被闭环调节消耗。超级PTAT电流源产生具有恒定斜率的超级PTAT电流，优异的稳定性和非常好的线性度。在一个实施例中，超级PTAT输出电流以预选比率与副PTAT电流混合，以产生具有所需温度系数的精确输出电流。

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