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81. 发明申请

US20080218282A1 Hybrid Stochastic Gradient Based Digitally Controlled Oscillator Gain KDCO Estimation 有权
标题翻译：混合随机梯度数字控制振荡器增益KDCO估计
公开(公告)号：US20080218282A1
公开(公告)日：2008-09-11
申请号：US12111813
申请日：2008-04-29
申请人： Khurram Waheed , Robert B. Staszewski
发明人： Khurram Waheed , Robert B. Staszewski
IPC分类号： H03L7/099
CPC分类号： H03B5/04 , H03L2207/50
摘要： A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.
摘要翻译：一种用于校准RF或非RF数字控制振荡器（DCO）的增益的新型混合随机梯度自适应装置和方法。自适应算法确定强制功能与其对应的系统测量之间的真实随机梯度，以估计适应的系统参数。产生动量项并将其注入到自适应算法中，以通过对输入数据中的任何大的瞬态变化添加惯性来稳定算法。在适应DCO增益K DC DC的情况下，算法确定时变校准或实际调制数据与在所有数字锁相环（ADPLL）中累积的原始相位误差之间的随机梯度。两个滤波器预处理可观测数据，以限制计算出的随机梯度的带宽，从而提供灵敏度和建立时间之间的折衷。

82. 发明申请

US20080192876A1 VARIABLE DELAY OSCILLATOR BUFFER 有权
标题翻译：可变延迟振荡器缓冲器
公开(公告)号：US20080192876A1
公开(公告)日：2008-08-14
申请号：US12021205
申请日：2008-01-28
申请人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
发明人： Fikret Dulger , Robert B. Staszewski , Francis P. Cruise , Gennady Feygin
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译：一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。抖动被转移到较高的频率，由PLL环路滤波器滤波。

83. 发明授权

US07405685B2 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
申请人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
发明人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

84. 发明申请

US20080072025A1 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US20080072025A1
公开(公告)日：2008-03-20
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F9/302 , G06F9/44
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

85. 发明申请

US20080068236A1 Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering 有权
标题翻译：自适应光谱噪声整形，以改善使用抖动的数字转换器量化分辨率的时间
公开(公告)号：US20080068236A1
公开(公告)日：2008-03-20
申请号：US11853182
申请日：2007-09-11
申请人： Mahbuba Moyeena Sheba , Robert B. Staszewski , Khurram Waheed
发明人： Mahbuba Moyeena Sheba , Robert B. Staszewski , Khurram Waheed
IPC分类号： H03M1/20 , H03M1/06
CPC分类号： G04F10/005
摘要： A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC quantization noise shaping scheme is effective to reduce the TDC quantization noise to acceptable levels especially in the case of integer-N channel operation. The mechanism monitors the output of the TDC circuit and adaptively generates a dither (i.e. delay) sequence based on the output. The dither sequence is applied to the frequency reference clock used in the TDC which adjusts the timing alignment between the edges of the frequency reference clock and the RF oscillator clock. The dynamic alignment changes effectively shape the quantization noise of the TDC. By shaping the quantization noise, a much finer in-band TDC resolution is achieved resulting in the quantization noise being pushed out to high frequencies where the PLL low pass characteristic effectively filters it out.
摘要翻译：一种用于提高使用噪声整形的数字PLL中的时间到数字转换器的量化分辨率的新颖有用的装置和方法。 TDC量化噪声整形方案有效地将TDC量化噪声降低到可接受的水平，特别是在整数N信道操作的情况下。该机制监视TDC电路的输出，并根据输出自适应地生成抖动（即延迟）序列。抖动序列被应用于TDC中使用的频率参考时钟，该频率参考时钟调整频率参考时钟的边沿与RF振荡器时钟之间的定时对准。动态对准改变有效地塑造了TDC的量化噪声。通过整形量化噪声，实现了更精细的带内TDC分辨率，导致量化噪声被推出到高频，其中PLL低通特性有效地滤除它。

86. 发明申请

US20080056337A1 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation 有权
标题翻译：使用异或运算，振荡器与RF频率之间具有非谐波比的本机振荡器
公开(公告)号：US20080056337A1
公开(公告)日：2008-03-06
申请号：US11844343
申请日：2007-08-23
申请人： Nir Tal , Yossi Tsfaty , Robert B. Staszewski , Gregory Lerner
发明人： Nir Tal , Yossi Tsfaty , Robert B. Staszewski , Gregory Lerner
IPC分类号： H04B1/40 , H03B21/00
CPC分类号： H03B21/02
摘要： A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. A synthesizer provides 4/3 the desired frequency fRF. This frequency is divided by two to obtain in-phase and quadrature square waves at ⅔ fRF. The in-phase signal is divided by two again to obtain in-phase and quadrature square waves at ⅓ fRF. The signals are then logically combined using XOR operations to obtain I and Q branch signals containing spectral spurs. Since the spurs are located in non-disturbing bands, they can be filtered out resulting in the desired output signal.
摘要翻译：本地振荡器（LO）生成的新颖有用的装置和方法，其本地振荡器和RF频率之间具有非整数倍乘比。所呈现的LO产生方案可用于以指定频率产生I和Q方波，同时避免众所周知的谐波拉动问题。合成器提供4/3所需的频率f RF。该频率除以2以在2/3 f RF RF获得同相和正交方波。同相信号再次被二分频以在1/3f RF RF下获得同相和正交方波。然后使用XOR操作逻辑地组合信号以获得包含光谱刺激的I和Q分支信号。由于马刺位于非干扰波段，所以它们可被滤除，从而产生所需的输出信号。

87. 发明申请

US20080055008A1 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation with jitter estimation and correction 有权
标题翻译：振荡器和RF频率之间具有非谐波比的本地振荡器，使用具有抖动估计和校正的异或运算
公开(公告)号：US20080055008A1
公开(公告)日：2008-03-06
申请号：US11844425
申请日：2007-08-24
申请人： Robert B. Staszewski , Nir Tal
发明人： Robert B. Staszewski , Nir Tal
IPC分类号： H03B21/01 , H03B21/00
CPC分类号： H03B21/00
摘要： A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.
摘要翻译：本地振荡器（LO）生成的新颖有用的装置和方法，其本地振荡器和RF频率之间具有非整数倍乘比。所呈现的LO产生方案可用于以指定频率产生I和Q方波，同时避免众所周知的谐波拉动问题。避免使用现有技术的模拟混频器，并用配置成产生正确的平均频率的XOR门代替。根据受控振荡器的分频时钟的状态，边沿被动态调整±T / 12或零。

88. 发明授权

US07330082B2 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US07330082B2
公开(公告)日：2008-02-12
申请号：US10924220
申请日：2004-08-23
申请人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
IPC分类号： H03B5/18
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：一种用于提供谐振信号的第n / O级振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括n + 并且被配置为通过将中间信号的复数滤波形式反馈到放大器来产生谐振信号。

89. 发明授权

US07292618B2 Fast hopping frequency synthesizer using an all digital phased locked loop (ADPLL) 有权
标题翻译：使用全数字锁相环（ADPLL）的快速跳频合成器
公开(公告)号：US07292618B2
公开(公告)日：2007-11-06
申请号：US11382570
申请日：2006-05-10
申请人： Nir Tal , Robert B. Staszewski , Ofer Friedman
发明人： Nir Tal , Robert B. Staszewski , Ofer Friedman
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/ƒT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译：一种新颖有用的快速频率合成器和发射机。频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / f T T中瞬时改变频率。在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。开关期间的任何相移都由发射机中的数字电路跟踪。在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。混频器在转换为数字域之前将波形应用于I和Q数据采样。

90. 发明申请

US20070190952A1 LINEARIZATION OF A TRANSMIT AMPLIFIER 有权
标题翻译：发射放大器的线性化
公开(公告)号：US20070190952A1
公开(公告)日：2007-08-16
申请号：US11675582
申请日：2007-02-15
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。本发明的机制利用在半双工操作期间的TX突发期间通常不工作的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准预失真表。受控RF耦合用于向接收机链提供RF输出信号的采样。预失真LUT的内容通常在PA上电或下降斜坡期间更新。当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算对预失真表的更新。

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