专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06658539B2 Super-coherent data mechanisms for shared caches in a multiprocessing system 有权
标题翻译：多处理系统中共享缓存的超连贯数据机制
公开(公告)号：US06658539B2
公开(公告)日：2003-12-02
申请号：US09978353
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/084
摘要： A method for improving performance of a multiprocessor data processing system having processor groups with shared caches. When a processor within a processor group that shares a cache snoops a modification to a shared cache line in a cache of another processor that is not within the processor group, the coherency state of the shared cache line within the first cache is set to a first coherency state that indicates that the cache line has been modified by a processor not within the processor group and that the cache line has not yet been updated within the group's cache. When a request for the cache line is later issued by a processor, the request is issued to the system bus or interconnect. If a received response to the request indicates that the processor should utilize super-coherent data, the coherency state of the cache line is set to a processor-specific super coherency state. This state indicates that subsequent requests for the cache line by the first processor should be provided said super-coherent data, while a subsequent request for the cache line by a next processor in the processor group that has not yet issued a request for the cache line on the system bus, may still go to the system bus to request the cache line. The individualized, processor-specific super coherency states are individually set but are usually changed to another coherency state (e.g., Modified or Invalid) as a group.
摘要翻译：一种用于改善具有处理器组与共享高速缓存的多处理器数据处理系统的性能的方法。当共享缓存的处理器组内的处理器窥探在处理器组内的另一处理器的高速缓存中的共享高速缓存线的修改时，第一高速缓存内的共享高速缓存行的一致性状态被设置为第一指示高速缓存行已被处理器组内的处理器修改并且高速缓存行尚未在组的高速缓存内更新的一致性状态。当稍后由处理器发出对高速缓存行的请求时，该请求被发布到系统总线或互连。如果对该请求的接收到的响应指示处理器应该使用超相干数据，则高速缓存行的一致性状态被设置为处理器特定的超一致性状态。该状态指示应该为所述超相干数据提供由第一处理器对高速缓存行的后续请求，而处理器组中尚未发出对高速缓存行请求的下一个处理器对高速缓存行的后续请求在系统总线上，仍然可以去系统总线请求缓存行。个性化的处理器特定的超一致性状态是单独设置的，但是通常作为一组更改为另一个一致性状态（例如，修改或无效）。

82. 发明授权

US5577231A Storage access authorization controls in a computer system using dynamic translation of large addresses 失效
标题翻译：使用大地址动态转换的计算机系统中的存储访问授权控制
公开(公告)号：US5577231A
公开(公告)日：1996-11-19
申请号：US349771
申请日：1994-12-06
申请人： Casper A. Scalzi , William J. Starke
发明人： Casper A. Scalzi , William J. Starke
IPC分类号： G06F9/455
CPC分类号： G06F9/45537
摘要： A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses "source effective addresses" (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).
摘要翻译：一种在计算机处理器中使用DAT机制来扩展以下两种方法：1）处理器的本地存储访问授权架构，以及2）使处理器能够执行设计为在不同存储访问架构下运行的程序。执行程序（称为源程序）在处理器（称为目标处理器）上执行时，使用“源有效地址”（源EA）来定位其指令和存储操作数。

83. 发明授权

US09619390B2 Proactive prefetch throttling 有权
公开(公告)号：US09619390B2
公开(公告)日：2017-04-11
申请号：US12649548
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
IPC分类号： G06F12/02 , G06F12/0862 , G06F12/0815
CPC分类号： G06F12/0862 , G06F12/0815
摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

84. 发明授权

US09176876B2 Selective cache-to-cache lateral castouts 有权
公开(公告)号：US09176876B2
公开(公告)日：2015-11-03
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

85. 发明授权

US08856455B2 Data cache block deallocate requests 有权
标题翻译：数据缓存块取消分配请求
公开(公告)号：US08856455B2
公开(公告)日：2014-10-07
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

86. 发明授权

US08656129B2 Aggregate symmetric multiprocessor system 失效
标题翻译：聚合对称多处理器系统
公开(公告)号：US08656129B2
公开(公告)日：2014-02-18
申请号：US13599891
申请日：2012-08-30
申请人： William J. Starke
发明人： William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F15/17337
摘要： An aggregate symmetric multiprocessor (SMP) data processing system includes a first SMP computer including at least first and second processing units and a first system memory pool and a second SMP computer including at least third and fourth processing units and second and third system memory pools. The second system memory pool is a restricted access memory pool inaccessible to the fourth processing unit and accessible to at least the second and third processing units, and the third system memory pool is accessible to both the third and fourth processing units. An interconnect couples the second processing unit in the first SMP computer for load-store coherent, ordered access to the second system memory pool in the second SMP computer, such that the second processing unit in the first SMP computer and the second system memory pool in the second SMP computer form a synthetic third SMP computer.
摘要翻译：聚合对称多处理器（SMP）数据处理系统包括包括至少第一和第二处理单元的第一SMP计算机和包括至少第三和第四处理单元以及第二和第三系统存储器池的第一系统存储器池和第二SMP计算机。第二系统存储器池是第四处理单元不可访问的受限访问存储器池，并且可由至少第二和第三处理单元访问，并且第三系统存储池可由第三处理单元和第四处理单元访问。互连耦合第一SMP计算机中的第二处理单元，用于对第二SMP计算机中的第二系统存储池进行加载存储一致的有序访问，使得第一SMP计算机中的第二处理单元和第二系统存储器池第二台SMP计算机形成了合成的第三台SMP计算机。

87. 发明授权

US08645633B2 Facilitating data coherency using in-memory tag bits and faulting stores 有权
标题翻译：使用内存中标记位和故障存储来促进数据一致性
公开(公告)号：US08645633B2
公开(公告)日：2014-02-04
申请号：US13109249
申请日：2011-05-17
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F9/4552 , G06F12/1045 , G06F2212/1008
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
摘要翻译：通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供原始数据的数据修改的细粒度检测。保护位有助于指示存储在相关联的颗粒中的原始数据是否被指示为受保护的。保护位通过专用指令进行设置和清除。响应于启动数据存储操作以修改原始数据，检查相关联的保护位以确定原始数据是否被指示为受保护的。响应于指示为相关联的原始数据设置了保护位的检查，修改原始数据的数据存储操作发生故障，并且转换的数据被丢弃，从而促进原始数据和转换的数据之间的数据一致性。

88. 发明申请

US20120324189A1 AGGREGATE DATA PROCESSING SYSTEM HAVING MULTIPLE OVERLAPPING SYNTHETIC COMPUTERS 有权
标题翻译：具有多重叠加合成计算机的综合数据处理系统
公开(公告)号：US20120324189A1
公开(公告)日：2012-12-20
申请号：US13599856
申请日：2012-08-30
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

89. 发明授权

US08103791B2 Synchronized communication in a data processing system 失效
标题翻译：数据处理系统中的同步通信
公开(公告)号：US08103791B2
公开(公告)日：2012-01-24
申请号：US12195130
申请日：2008-08-20
申请人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F15/173 , G06F12/00 , G06F13/14 , G06F1/04 , G06F1/12
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.
摘要翻译：数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。

90. 发明授权

US08095733B2 Virtual barrier synchronization cache castout election 失效
标题翻译：虚拟屏障同步缓存突发选举
公开(公告)号：US08095733B2
公开(公告)日：2012-01-10
申请号：US12419343
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路，第二和第三处理单元。通过互连结构上的选举来转移责任。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式