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81. 发明申请

US20070224756A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE 审中-公开
标题翻译：用于制造接收栅极MOS晶体管器件的方法
公开(公告)号：US20070224756A1
公开(公告)日：2007-09-27
申请号：US11456856
申请日：2006-07-11
申请人： Yu-Pi Lee , Shian-Jyh Lin
发明人： Yu-Pi Lee , Shian-Jyh Lin
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10861 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating self-aligned gate trench utilizing TTO spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Spacers are formed on the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO间隔件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。沟槽电容器形成在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。在挤出TTO上形成间隔物，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

82. 发明申请

US20070096186A1 Vertical transistor device and fabrication method thereof 审中-公开
标题翻译：垂直晶体管器件及其制造方法
公开(公告)号：US20070096186A1
公开(公告)日：2007-05-03
申请号：US11366107
申请日：2006-03-01
申请人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih
发明人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10841 , H01L27/10867
摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.
摘要翻译：提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。电容器设置在深沟槽的下部。导电结构设置在深沟槽内的电容器上。具有外延侧壁区域的外延层设置在基板上。垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

83. 发明授权

US07205075B2 Method of forming a vertical memory device with a rectangular trench 有权
标题翻译：形成具有矩形沟槽的垂直存储器件的方法
公开(公告)号：US07205075B2
公开(公告)日：2007-04-17
申请号：US10448675
申请日：2003-05-29
申请人： Yu-Sheng Shu , Yuan-Hsun Wu , Chung-Yuan Lee , Shian-Jyh Lin
发明人： Yu-Sheng Shu , Yuan-Hsun Wu , Chung-Yuan Lee , Shian-Jyh Lin
IPC分类号： G03F1/00
CPC分类号： H01L27/1087 , H01L21/3083 , H01L27/0207 , H01L27/10864
摘要： A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.
摘要翻译：一种形成具有矩形沟槽的垂直存储器件的方法。首先，提供由光致抗蚀剂层覆盖的基板。接下来，通过掩模限定光致抗蚀剂层以形成矩形开口，其中掩模具有以预定间隔布置的两个矩形透明图案。接下来，使用限定的光致抗蚀剂层作为掩模来蚀刻基板以形成单个矩形沟槽，然后除去光致抗蚀剂层。最后，在矩形沟槽中依次形成沟槽电容器和垂直晶体管，以完成垂直存储器件。

84. 发明授权

US06992021B2 Method for forming a silicon nitride layer 有权
标题翻译：形成氮化硅层的方法
公开(公告)号：US06992021B2
公开(公告)日：2006-01-31
申请号：US10620518
申请日：2003-07-16
申请人： Shian-Jyh Lin , Hai-Han Hung , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Hai-Han Hung , Chung-Yuan Lee
IPC分类号： H01L21/39 , H01L21/469
CPC分类号： H01L29/66181 , C23C14/0652 , C23C14/48 , H01L21/26506 , H01L21/3185
摘要： A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.
摘要翻译：一种形成氮化硅层的方法。该方法包括提供其上具有硅表面的衬底，在硅表面上执行离子注入工艺，将氮原子注入到硅表面中，以及执行热氮化工艺并在衬底上形成氮化硅层，其中氮化硅层包括通过硅表面与其中包含的氮原子的反应在硅表面上形成的氮化硅。

85. 发明授权

US06977227B2 Method of etching bottle trench and fabricating capacitor with same 有权
标题翻译：蚀刻瓶沟槽的方法和制造与之相同的电容器
公开(公告)号：US06977227B2
公开(公告)日：2005-12-20
申请号：US10871619
申请日：2004-06-18
申请人： Shian-Jyh Lin , Yu-Sheng Hsu , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Yu-Sheng Hsu , Chung-Yuan Lee
IPC分类号： H01L21/033 , H01L21/20 , H01L21/308 , H01L21/311 , H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L21/0337 , H01L21/3086 , H01L29/66181 , H01L29/945
摘要： A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.
摘要翻译：一种形成瓶槽的方法。首先，在进行光刻之前，将由光致抗蚀剂层覆盖的基板旋转到特定角度，从而在光致抗蚀剂层中形成矩形开口并暴露基板，其中矩形开口的边缘基本上平行于{110} 由于基板的旋转而导致基板的平面。接下来，暴露的衬底被蚀刻以在其中形成沟槽，其中沟槽的侧壁表面是衬底的{110}平面。最后，使用形成在沟槽的上部的侧壁上的蚀刻屏蔽层作为蚀刻掩模，在沟槽的下部的基板上进行各向同性蚀刻，以形成瓶沟槽。本发明还公开了一种制造瓶沟电容器的方法。

86. 发明申请

US20050208775A1 METHOD FOR GROWING A GATE OXIDE LAYER ON A SILICON SURFACE WITH PRELIMINARY N2O ANNEAL 审中-公开
标题翻译：在具有初步N2O阳极的硅表面上生长栅氧化层的方法
公开(公告)号：US20050208775A1
公开(公告)日：2005-09-22
申请号：US10711178
申请日：2004-08-30
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： G01R31/26 , H01L21/28 , H01L21/31 , H01L21/316 , H01L21/469 , H01L21/66
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02312 , H01L21/2822 , H01L21/31662
摘要： The present invention relates to a method for growing a robust, high-quality gate oxide layer on a silicon surface. The resultant gate oxide layer made according to the present invention can pass the standard 50K times 14V high-voltage stress testing. The preferred embodiment of this invention includes a step of preliminary low-pressure N2O annealing that is carried out in an air-tight chamber at a temperature of less than 1000° C., a pressure below 0.2 torr, and N2O flow rate of below 8000 sccm. The preliminary low-pressure N2O annealing of the silicon surface is performed prior to the growth of high-quality gate oxide layer. In another preferred embodiment, N2O may be replaced with NO.
摘要翻译：本发明涉及一种用于在硅表面上生长坚固，高质量的栅氧化层的方法。根据本发明制成的栅极氧化物层可以通过标准的50K倍的14V高压应力测试。本发明的优选实施方案包括在低于1000℃的温度，压力低于0.2的气密室中进行的初步低压N 2 O 2退火步骤托辊和N 2 O 2流量低于8000sccm。硅表面的初步低压N 2 O 2退火在高品质栅极氧化物层的生长之前进行。在另一优选实施方案中，N 2 O可以被NO代替。

87. 发明申请

US20050205942A1 METAL GATE WITH COMPOSITE FILM STACK 有权
标题翻译：金属门与复合膜片
公开(公告)号：US20050205942A1
公开(公告)日：2005-09-22
申请号：US10708708
申请日：2004-03-19
申请人： Shian-Jyh Lin , Chung-Yuan Lee , Yu-Chang LIN
发明人： Shian-Jyh Lin , Chung-Yuan Lee , Yu-Chang LIN
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6656 , H01L21/28061 , H01L29/4941 , H01L29/78
摘要： A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked on the CVD ultra-thin titanium nitride film, a tungsten layer stacked on the tungsten nitride layer, and a nitride cap layer stacked on the tungsten layer. A liquid phase deposition (LPD) oxide spacer is formed on each sidewall of the metal gate stack. A silicon nitride spacer is formed on the LPD oxide spacer. The thickness of the CVD ultra-thin titanium nitride film is between 10 and 100 angstroms.
摘要翻译：一种新颖的金属栅极结构，包括形成在硅衬底的表面上的栅极氧化层，堆叠在栅极氧化物层上的掺杂硅层，沉积在掺杂硅层上的CVD超薄氮化钛膜，堆叠的氮化钨层在CVD超薄氮化钛膜上堆叠在钨氮化物层上的钨层和层叠在钨层上的氮化物盖层。在金属栅极堆叠的每个侧壁上形成液相沉积（LPD）氧化物间隔物。在LPD氧化物间隔物上形成氮化硅间隔物。 CVD超薄氮化钛膜的厚度为10〜100埃。

88. 发明申请

US20050164446A1 Method for manufacturing single-sided buried strap in semiconductor devices 有权
标题翻译：在半导体器件中制造单面埋入带的方法
公开(公告)号：US20050164446A1
公开(公告)日：2005-07-28
申请号：US10940761
申请日：2004-09-15
申请人： Shian-Jyh Lin , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/306 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244
CPC分类号： H01L27/10867
摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.
摘要翻译：公开了一种制造半导体器件中使用的单端掩埋带的方法。根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。然后，在凹部的侧壁上形成绝缘层。接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

89. 发明申请

US20130153982A1 SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF 有权
公开(公告)号：US20130153982A1
公开(公告)日：2013-06-20
申请号：US13325063
申请日：2011-12-14
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

90. 发明授权

US08202801B1 Method of fabricating a semiconductor device with through substrate via 有权
标题翻译：制造具有贯通基板通孔的半导体器件的方法
公开(公告)号：US08202801B1
公开(公告)日：2012-06-19
申请号：US13400592
申请日：2012-02-21
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L21/44
CPC分类号： H01L23/481 , H01L21/76898 , H01L25/0657 , H01L2224/94 , H01L2225/06544 , H01L2924/01019 , H01L2924/09701
摘要： A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
摘要翻译：提供了具有低应力的贯通基板通孔。贯通基板通孔位于基板中。贯通基板通孔包括：穿过基板的外管; 设置在所述外管内的至少一个内管; 在外管的侧壁上衬有的电介质层和内管的侧壁; 填充内管的强度增强材料; 以及填充外管的导电层。

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