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81. 外观设计

USD607109S1 Dental equipment 有权
标题翻译：牙科设备
公开(公告)号：USD607109S1
公开(公告)日：2009-12-29
申请号：US29323080
申请日：2008-08-18
申请人： David Lewis
设计人： David Lewis

82. 发明申请

US20090289696A1 Apparatus and Methods for Adjusting Performance of Integrated Circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US20090289696A1
公开(公告)日：2009-11-26
申请号：US12534101
申请日：2009-07-31
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

83. 发明授权

US07619443B1 Programmable logic device architectures and methods for implementing logic in those architectures 有权
标题翻译：可编程逻辑器件架构和方法，用于在这些架构中实现逻辑
公开(公告)号：US07619443B1
公开(公告)日：2009-11-17
申请号：US11356762
申请日：2006-02-16
申请人： Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
发明人： Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.
摘要翻译：可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LABs“）的集群在一起的逻辑元件（”LE“）。为了保存区域，本地反馈资源（用于将LAB中的LE的输出馈送回到与现有技术相比，减少或消除了LAB中的LE的输入），因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须是通过LAB的通用输入路由资源路由，重要的是保存这些资源，例如，通过更加重视找到具有共同输入的逻辑功能，在决定在劳顾会

84. 发明授权

US07573317B2 Apparatus and methods for adjusting performance of integrated circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US07573317B2
公开(公告)日：2009-08-11
申请号：US11535065
申请日：2006-09-26
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

85. 发明授权

US07538579B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07538579B1
公开(公告)日：2009-05-26
申请号：US11607171
申请日：2006-12-01
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

86. 外观设计

USD582364S1 Television 有权
公开(公告)号：USD582364S1
公开(公告)日：2008-12-09
申请号：US29307416
申请日：2008-04-18
申请人： David Lewis
设计人： David Lewis

87. 发明申请

US20080218197A1 PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRANULARITY 有权
标题翻译：具有逻辑元素冗余的可编程逻辑器件
公开(公告)号：US20080218197A1
公开(公告)日：2008-09-11
申请号：US11739055
申请日：2007-04-23
申请人： David Lewis , David Cashman
发明人： David Lewis , David Cashman
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , H03K19/00392 , H03K19/17728
摘要： A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element.
摘要翻译：公开了具有逻辑元件行粒度冗余的PLD。 PLD包括布置在阵列中的多个LAB以及互连阵列的LAB的多个水平和垂直的LAB线。每个LAB还包括预定数量的逻辑元件和冗余电路，以通过将用于故障逻辑元件的编程数据移位到无缺陷逻辑来在预定逻辑元件中用无缺陷逻辑元件代替故障逻辑元件元件。

88. 发明授权

US07391236B2 Distributed memory in field-programmable gate array integrated circuit devices 有权
公开(公告)号：US07391236B2
公开(公告)日：2008-06-24
申请号：US11320253
申请日：2005-12-27
申请人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
发明人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
IPC分类号： H03K19/177
CPC分类号： G11C7/1045 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

89. 发明授权

US07381402B2 Stable pharmaceutical solution formulations for pressurized metered dose inhalers 失效
标题翻译：用于加压计量剂量吸入器的稳定的药物溶液制剂
公开(公告)号：US07381402B2
公开(公告)日：2008-06-03
申请号：US11065569
申请日：2005-02-25
申请人： David Lewis , David Ganderton , Brian Meakin , Maurizio Delcanale , Fausto Pivetti
发明人： David Lewis , David Ganderton , Brian Meakin , Maurizio Delcanale , Fausto Pivetti
IPC分类号： A61K9/12 , A61K9/08 , A61K31/47 , A61K31/4704 , A61M11/00 , A61M11/04 , A61M15/00 , A61M15/06
CPC分类号： A61K9/008 , A61K31/137 , A61K31/47 , A61K31/4704 , A61K47/02 , A61M15/009 , A61M2205/0222 , A61K2300/00
摘要： Aerosol solution formulations for use in an aerosol inhaler which comprise 8-hydroxy-5-[(1R)-1-hydroxy-2-[[(1R)-2-(4-methoxyphenyl)-1-methylethyl]amino]-ethyl]-2(1H)-quinolinone or a salt thereof, in particular the hydrochloride salt (TA 2005), as an active ingredient, a propellant containing a hydrofluoroalkane, and a cosolvent, stabilized by addition of a specific small amount of a high concentrated phosphoric acid exhibit improved shelf life. The formulation may be optionally contained in a can having part or all of its internal metallic surfaces lined with an inert organic coating.
摘要翻译：用于气溶胶吸入器的气溶胶溶液制剂，其包含8-羟基-5 - [（1R）-1-羟基-2 - [[（1R）-2-（4-甲氧基苯基）-1-甲基乙基]氨基] - 乙基 ] -2（1H） - 喹啉酮或其盐，特别是盐酸盐（TA 2005）作为活性成分，含有氢氟烷烃和助溶剂的推进剂，通过加入特定量的高浓度磷酸表现出改善的保质期。制剂可以任选地包含在其内部具有惰性有机涂层的部分或全部内部金属表面的罐中。

90. 发明申请

US20080089603A1 METHOD FOR REMOVING THE EFFECT OF LIGHT SCATTERING IN A DIGITIZED IMAGE OF A LIGHT-SCATTERING FILM 有权
标题翻译：光散射对光散射影像的影像的影响的方法
公开(公告)号：US20080089603A1
公开(公告)日：2008-04-17
申请号：US11836389
申请日：2007-08-09
申请人： David Lewis , Loris Menegotti , Anna Delana
发明人： David Lewis , Loris Menegotti , Anna Delana
IPC分类号： G06K9/40
CPC分类号： G06T5/002 , G06T5/50 , G06T2207/10008
摘要： In accordance with the present invention, there is provided a method for removing the effect of light scattering in a digitized image of a light-scattering film comprising providing a light-scattering correction film that has a uniform optical density; providing a light scattering target film that has a pattern of optical densities; scanning the correction film with a film scanner to create a digital correction film image; scanning the target film with a film scanner to create a digital target film image; measuring the two-dimensional pattern of responses present in the digital correction film image; determining a correction function from the two-dimensional pattern of responses to correct for the effect of light scattering in the digital correction film image; and applying the correction function to the target film image to provide a corrected target film image.
摘要翻译：根据本发明，提供了一种去除光散射膜的数字化图像中的光散射效应的方法，包括提供具有均匀光密度的光散射校正膜; 提供具有光密度图案的光散射目标膜; 用胶片扫描仪扫描校正膜以产生数字校正胶片图像; 用胶片扫描仪扫描目标胶片以创建数字目标胶片图像; 测量数字校正胶片图像中存在的响应的二维图案; 从响应的二维图案确定校正函数，以校正数字校正膜图像中光散射的影响; 以及将校正功能应用于目标胶片图像以提供校正的目标胶片图像。

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