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81. 发明申请

WO2017171866A1 INTEGRATED 1T1R RRAM MEMORY CELL 审中-公开
标题翻译：集成的1T1R RRAM存储器单元
公开(公告)号：WO2017171866A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025694
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , PILLARISETTY, Ravi , MAJHI, Prashant , MUKHERJEE, Niloy , SHAH, Uday
IPC分类号： G11C13/00 , G06F12/02
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/53 , G11C2213/73 , G11C2213/74 , G11C2213/79 , G11C2213/82 , H01L27/2445
摘要： One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.
摘要翻译：一个实施例提供了一种装置。该装置包括双极结型晶体管（BJT）和集成电阻元件。 BJT包括基极触点，基极区域，集电极触点，集电极区域和集成发射极触点。集成电阻元件包括电阻层和集成电极。电阻元件位于基极区和集成发射极触点之间。

82. 发明申请

WO2017171820A1 MULTILAYER SELECTOR DEVICE WITH LOW LEAKAGE CURRENT 审中-公开
标题翻译：具有低漏电流的多层选择器装置
公开(公告)号：WO2017171820A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025433
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , MAJHI, Prashant , PILLARISETTY, Ravi , SHAH, Uday , CLARKE, James S.
IPC分类号： H01L45/00 , H01L45/02 , G11C13/00
CPC分类号： H01L27/2427 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/51 , G11C2213/52 , G11C2213/53 , G11C2213/54 , G11C2213/76 , G11C2213/79 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608
摘要： An embodiment includes an apparatus comprising: first and second electrodes; first and second insulation layers between the first and second electrodes; and a middle layer between the first and second insulation layers; wherein (a) the middle layer includes material that has a first resistance when the first electrode is biased at a first voltage level and a second resistance when the first electrode is biased at a second voltage level; (b) the first resistance is less than the second resistance and the first voltage level is greater than the second voltage level. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，该装置包括：第一和第二电极; 在第一和第二电极之间的第一和第二绝缘层; 以及第一和第二绝缘层之间的中间层; 其中（a）所述中间层包括当所述第一电极被偏置在第一电压电平时具有第一电阻并且当所述第一电极被偏置在第二电压电平时具有第二电阻的材料; （b）第一电阻小于第二电阻并且第一电压电平大于第二电压电平。这里描述了其他实施例。

83. 发明申请

WO2017111812A1 RRAM BASED COMPLIMENTARY SWITCH FOR CROSSPOINT MEMORY APPLICATIONS 审中-公开
标题翻译：基于RRAM的交叉存储器应用的免疫开关
公开(公告)号：WO2017111812A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000368
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , KARPOV, Elijah V. , MAJHI, Prashant , SHAH, Uday , MUKHERJEE, Niloy
IPC分类号： H01L45/00 , H01L45/02
CPC分类号： H01L45/146 , H01L45/08 , H01L45/1675
摘要： An embodiment includes a resistive random access memory (RRAM) system comprising: a bi-polar complimentary resistive switch (CRS) comprising a top electrode, a bottom electrode, and an oxide layer between the top and bottom electrodes; wherein (a) a first plurality of oxygen vacancies are within the oxide layer and are adjacent the top electrode at a first concentration, (b) a second plurality of oxygen vacancies are within the oxide layer and are adjacent the bottom electrode at a second concentration, and (c) a third plurality of oxygen vacancies are within the oxide layer at a third concentration and between the first and second pluralities of oxygen vacancies. Other embodiments are described herein.
摘要翻译：一个实施例包括电阻式随机存取存储器（RRAM）系统，其包括：双极互补电阻式开关（CRS），其包括顶部电极，底部电极以及在顶部和底部之间的氧化物层电极; 其中（a）第一多个氧空位在氧化物层内并且以第一浓度与顶电极相邻，（b）第二多个氧空位在氧化物层内且在第二浓度下与底电极相邻（c）第三多个氧空位在第三浓度的氧化物层内以及第一和第二多个氧空位之间。这里描述了其他实施例。

84. 发明申请

WO2017052565A1 SELF-ALIGNED MEMORY ARRAY 审中-公开
标题翻译：自对准存储阵列
公开(公告)号：WO2017052565A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052051
申请日：2015-09-24
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , SHAH, Uday , PILLARISETTY, Ravi , DOYLE, Brian S.
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1659 , H01L27/224 , H01L43/08 , H01L43/12
摘要： An embodiment includes a memory array comprising: a memory cell including a switch stack in series with a memory stack; and a bit line above the memory cell and a word line below the memory cell; wherein (a) first switch stack sidewalls of the switch stack are vertically aligned with bit line sidewalls of the bit line and second switch stack sidewalls of the switch stack are vertically aligned with word line sidewalls of the word line; (b) first memory stack sidewalls of the memory stack are vertically aligned with the bit line sidewalls and second memory stack sidewalls of the memory stack are vertically aligned with the word line sidewalls. Other embodiments are described herein.
摘要翻译：实施例包括存储器阵列，其包括：存储器单元，其包括与存储器堆叠串联的开关堆叠; 以及位于存储器单元之上的位线和存储器单元下方的字线; 其中（a）开关堆叠的第一开关堆叠侧壁与位线的位线侧壁垂直对准，并且开关堆叠的第二开关堆叠侧壁与字线的字线侧壁垂直对准; （b）存储器堆叠的第一存储器堆叠侧壁与位线侧壁垂直对准，并且存储器堆叠的第二存储器堆叠侧壁与字线侧壁垂直对准。本文描述了其它实施例。

85. 发明申请

WO2016204750A1 RANDOM NUMBER GENERATOR 审中-公开
标题翻译：随机数发电机
公开(公告)号：WO2016204750A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036266
申请日：2015-06-17
申请人： INTEL CORPORATION
发明人： KUO, Charles C. , BROCKMAN, Justin S. , ALZATE VINASCO, Juan G. , OGUZ, Kaan , O'BRIEN, Kevin P. , DOYLE, Brian S. , DOCZY, Mark L. , SURI, Satyarth , CHAU, Robert S. , MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V.
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H01L43/02 , H01L43/08
摘要： Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.
摘要翻译：描述了一种装置，其包括：磁隧道结（MTJ）装置，其具有用于其自由和固定磁性层的平面外磁化，并且被配置为具有远离中心的磁化偏移并且更接近MTJ的切换阈值设备; 以及根据MTJ设备的电阻状态产生随机数的逻辑。

86. 发明申请

WO2014098969A1 PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME 审中-公开
标题翻译：具有增强稳定性的全速转子扭矩记忆（STTM）装置及其形成方法
公开(公告)号：WO2014098969A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/045498
申请日：2013-06-12
申请人： INTEL CORPORATION
发明人： DOYLE, Brian S. , KUO, Charles C. , OGUZ, Kaan , SHAH, Uday , KARPOV, Elijah V. , MOJARAD, Roksana Golizadeh , DOCZY, Mark L. , CHAU, Robert S.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L43/10 , G11C11/161 , G11C11/18 , H01F10/14 , H01F10/16 , H01F10/1936 , H01F10/3236 , H01F10/3286 , H01F10/329 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
摘要翻译：描述了具有增强的稳定性的垂直自旋转移转矩存储器（STTM）装置和制造具有增强的稳定性的垂直STTM装置的方法。例如，用于磁隧道结的材料层堆叠包括固定磁性层。电介质层设置在固定磁性层的上方。自由磁性层设置在电介质层的上方。导电氧化物材料层设置在自由磁性层上。

87. 发明申请

WO2014084909A1 LOW VOLTAGE EMBEDDED MEMORY HAVING CATIONIC-BASED CONDUCTIVE OXIDE ELEMENT 审中-公开
标题翻译：具有基于阳离子的导电氧化物元件的低电压嵌入式存储器
公开(公告)号：WO2014084909A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/047418
申请日：2013-06-24
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , DOYLE, Brian S. , KUO, Charles C. , CHAU, Robert S.
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L45/085 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/2436 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.
摘要翻译：描述了具有阳离子基导电氧化物元件的低电压嵌入式存储器。例如，用于存储元件的材料层堆叠包括第一导电电极。阳离子基导电氧化物层设置在第一导电电极上。阳离子型导电氧化物层中具有多个阳离子空位。第二电极设置在阳离子基导电氧化物层上。

88. 发明公开

EP3629381A1 TRANSISTORS WITH FERROELECTRIC GATES 有权
公开(公告)号：EP3629381A1
公开(公告)日：2020-04-01
申请号：EP19182447.3
申请日：2019-06-25
申请人： INTEL Corporation
发明人： SHARMA, Abhishek A. , PILLARISETTY, Ravi , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant , DEWEY, Gilbert W. , CHU-KUNG, Benjamin , LE, Van H. , KAVALIEROS, Jack T. , GHANI, Tahir
IPC分类号： H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786
摘要： Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

89. 发明授权

EP2901454B1 DECREASED SWITCHING CURRENT IN SPIN-TRANSFER TORQUE MEMORY 有权转让
公开(公告)号：EP2901454B1
公开(公告)日：2018-10-10
申请号：EP13840358.9
申请日：2013-06-10
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , DOYLE, Brian S. , OGUZ, Kaan , SURI, Satyarth , CHAU, Robert S. , KUO, Charles C. , DOCZY, Mark L. , KENCKE, David L.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , B82Y25/00 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/5607 , H01F10/3254 , H01L27/222 , H01L43/02 , H01L43/08
摘要： Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.

90. 发明公开

EP3161867A1 OXIDE-BASED THREE-TERMINAL RESISTIVE SWITCHING LOGIC DEVICES 有权
标题翻译：基于氧化物的三端电阻切换逻辑器件
公开(公告)号：EP3161867A1
公开(公告)日：2017-05-03
申请号：EP14895579.2
申请日：2014-06-26
申请人： Intel Corporation
发明人： KARPOV, Elijah V. , MAJHI, Prashant , PILLARISETTY, Ravi , DOYLE, Brian S. , MUKHERJEE, Niloy , SHAH, Uday , CHAU, Robert S.
IPC分类号： H01L27/115 , H01L29/02
CPC分类号： H01L45/1206 , H01L29/45 , H01L29/4908 , H01L29/78618 , H01L29/7869 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.
摘要翻译：描述了基于氧化物的三端电阻切换逻辑器件和制造基于氧化物的三端电阻切换逻辑器件的方法。在第一示例中，三端子电阻切换逻辑器件包括设置在衬底上方的有源区。有源区包括直接设置在金属源极区和金属漏极区之间的有源氧化物材料区。该器件还包括设置在有源氧化物材料区域上方的栅电极。在第二示例中，三端子电阻切换逻辑器件包括设置在衬底上方的有源区。有源区包括与第二氧化物材料区隔开的第一有源氧化物材料区。该器件还包括设置在第一和第二活性氧化物材料区域的任一侧上的金属输入区域。金属输出区域设置在第一和第二有源氧化物材料区域之间。

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