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81. 发明授权

US08183618B2 Method for fabricating a charge trapping memory device 有权
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US08183618B2
公开(公告)日：2012-05-22
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

82. 发明授权

US08022465B2 Low hydrogen concentration charge-trapping layer structures for non-volatile memory 有权
标题翻译：用于非易失性存储器的低氢浓度电荷捕获层结构
公开(公告)号：US08022465B2
公开(公告)日：2011-09-20
申请号：US11274781
申请日：2005-11-15
申请人： Yen-Hao Shih , Min-Ta Wu , Shin-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shin-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

83. 发明授权

US07977227B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07977227B2
公开(公告)日：2011-07-12
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

84. 发明授权

US07778072B2 Method for fabricating charge-trapping memory 有权
标题翻译：电荷捕获存储器的制造方法
公开(公告)号：US07778072B2
公开(公告)日：2010-08-17
申请号：US11460497
申请日：2006-07-27
申请人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
发明人： Yen-Hao Shih , Jung-Yu Hsieh , Yi-Lin Yang , Chia-Hua Chang , Jenn-Gwo Hwu
IPC分类号： G11C11/34
CPC分类号： H01L21/76838 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a temperature of about 350° C. to 450° C. and with the concentration of the hydrogen gas greater than 0.5 mole percent.
摘要翻译：提供了一种电荷俘获存储器件的制造方法。该方法包括形成至少具有电荷捕获介质的堆叠结构。然后在器件制造过程之后对堆叠结构进行氢气中的退火处理。退火过程在约350℃至450℃的温度下进行，氢气的浓度大于0.5摩尔％。

85. 发明授权

US07582526B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07582526B2
公开(公告)日：2009-09-01
申请号：US11445870
申请日：2006-06-02
申请人： Yen-Hao Shih , Erh-Kun Lai
发明人： Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11546 , H01L27/11568 , H01L29/78
摘要： A method for manufacturing a plurality of memory devices and a plurality of high voltage devices on a substrate are provided. The substrate has a memory region and a high voltage region. The method comprises steps of forming a first dielectric layer on the substrate and then performing a thermal process so as to enlarge the thickness of the first dielectric layer in the high voltage region. A buried diffusion region is formed in the substrate in the memory region and a charge trapping layer and a blocking dielectric layer are formed over the substrate in the memory region. A patterned conductive layer is formed over the substrate so as to form gates the memory region and the high voltage region respectively and then a source/drain region is formed adjacent to the gates in the high voltage region in the substrate.
摘要翻译：提供了一种用于在基板上制造多个存储器件和多个高电压器件的方法。衬底具有存储区和高电压区。该方法包括以下步骤：在衬底上形成第一电介质层，然后进行热处理，以扩大高电压区域中的第一电介质层的厚度。在存储区中的衬底中形成掩埋扩散区，并且在存储区中的衬底上形成电荷俘获层和阻挡电介质层。在衬底上形成图案化的导电层，以分别形成存储区域和高电压区域的栅极，然后在衬底中的高电压区域中邻近栅极形成源极/漏极区域。

86. 发明申请

US20090108331A1 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US20090108331A1
公开(公告)日：2009-04-30
申请号：US11979101
申请日：2007-10-31
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
摘要翻译：提供具有隔离双存储单元的存储器。第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

87. 发明授权

US07414282B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07414282B2
公开(公告)日：2008-08-19
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

88. 发明授权

US07329914B2 Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same 有权
标题翻译：具有两个分离的非导电电荷捕获插入物的电荷俘获存储器件及其制造方法
公开(公告)号：US07329914B2
公开(公告)日：2008-02-12
申请号：US10884483
申请日：2004-07-01
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.
摘要翻译：公开了具有两个分开的非导电电荷捕获插入物的电荷捕获存储器件。电荷捕获存储器件具有带有两个结的硅衬底。在硅衬底的顶部和两个结之间形成栅极氧化物（GOX）。在GOX上定义了多晶硅栅极。在硅衬底的顶部上生长一层底部氧化物（BOX），沿多晶硅栅极的底部和侧壁生长顶部氧化物（TOX）的共形层。两个充电陷阱插件位于GOX旁边和BOX和TOX之间。多晶硅栅极需要至少部分地在两个电荷捕获插入物中的每一个上。电荷捕获插入物由非导电电荷捕获材料制成。还描述了制造这种装置的方法。

89. 发明申请

US20070293006A1 METHOD FOR FABRICATING A CHARG TRAPPING MEMORY DEVICE 有权
标题翻译：一种用于制作电荷捕捉存储器件的方法
公开(公告)号：US20070293006A1
公开(公告)日：2007-12-20
申请号：US11425160
申请日：2006-06-20
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

90. 发明申请

US20070259495A1 A NON-VOLATILE MEMORY DEVICE INCLUDING NITROGEN POCKET IMPLANTS AND METHODS FOR MAKING THE SAME 有权
标题翻译：包括氮气口植入物的非易失性存储器件及其制造方法
公开(公告)号：US20070259495A1
公开(公告)日：2007-11-08
申请号：US11381307
申请日：2006-05-02
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.
摘要翻译：在非易失性存储器结构中，源极/漏极区域被氮掺杂区域包围。结果，在氮掺杂区上方的衬底和电荷俘获层之间的界面被多个氮原子钝化。氮原子可以提高循环非易失性存储器件的数据保留性能和性能。

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