专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20060218988A1 EXHAUST GAS MEASURING DEVICE AND METHOD FOR MEASURING EXHAUST GAS 有权
标题翻译：排气测量装置和测量排气的方法
公开(公告)号：US20060218988A1
公开(公告)日：2006-10-05
申请号：US11278605
申请日：2006-04-04
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G01N33/497
CPC分类号： G01M15/102 , G01N33/004 , Y02A50/243 , Y02A50/244
摘要： With the exhaust gas measuring device and the exhaust gas measuring method, the workload of the internal combustion engine is calculated based on a discharged amount of a component related to a carbon compound such as CO, CO2 and THC in the exhaust gas discharged from the internal combustion engine. As a result, the workload of the internal combustion engine can be calculated easily without using torque data of the ECU and the mass of each component in the exhaust gas discharged from the internal combustion engine per unit workload can be calculated.
摘要翻译：利用废气测量装置和废气测量方法，基于与CO，CO 2和THC等碳化合物相关的成分的排出量来计算内燃机的工作量在从内燃机排出的废气中。结果，能够容易地计算内燃机的工作量，而不需要使用ECU的转矩数据，并且可以计算出每单位工作量从内燃机排放的废气中的每个部件的质量。

82. 发明申请

US20060175414A1 Method for reading out symbol information and device for reading out symbol information 有权
标题翻译：用于读出符号信息的方法和用于读出符号信息的装置
公开(公告)号：US20060175414A1
公开(公告)日：2006-08-10
申请号：US11316546
申请日：2005-12-21
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G06K7/10
CPC分类号： G06K7/1456 , G06K7/14 , G06K7/1486
摘要： To provide a method for reading out symbol information and a device for reading out symbol information which are able to prevent a decline in decoding reliability by reducing noise caused by a quantized error, localized contaminations or the like. The method for reading out symbol information may comprise a process in which the image data, obtained by imaging the symbol information such as bar codes and the like, are converted to corrected image data having zero angle of inclination; a smoothing process in which the corrected image data are smoothed; and a column specifying process in which breakpoints of said symbol information column are specified by computing the total sum in the row direction on the smoothed corrected image data.
摘要翻译：提供一种读出符号信息的方法和用于读出能够通过减少由量化误差，局部污染等引起的噪声而能够防止解码可靠性下降的符号信息的装置。用于读出符号信息的方法可以包括将通过对诸如条形码等的符号信息进行成像而获得的图像数据转换为具有零倾角的校正图像数据的处理; 平滑处理，其中校正的图像数据被平滑化; 以及列指定处理，其中通过计算平滑校正图像数据上的行方向上的总和来指定所述符号信息列的断点。

83. 发明授权

US07076926B2 Damping intermediate pillar and damping structure using the same 有权
标题翻译：阻尼中柱和阻尼结构使用相同
公开(公告)号：US07076926B2
公开(公告)日：2006-07-18
申请号：US10213201
申请日：2002-08-06
申请人： Kazuhiko Kasai , Hiroshi Nakamura , Yasuhiro Nakata , Takashi Shirai
发明人： Kazuhiko Kasai , Hiroshi Nakamura , Yasuhiro Nakata , Takashi Shirai
IPC分类号： E04H9/02 , E04B1/98
CPC分类号： E04H9/02 , E04B2001/2415 , E04B2001/2442 , E04B2001/2445 , E04B2001/2448
摘要： A damping intermediate pillar, which can exhibit a sufficient resistance against the horizontal force of a strong earthquake by reinforcing the joins between the damping intermediate pillar and the upper and lower beams, is disclosed. A damping intermediate pillar 14, used for a building or a structure configured of pillars 1 and beams 3, is divided into upper and lower damping intermediate pillar portions 14a, 14b of H shape steel, and includes a plurality of inner steel plates 7b fixed on the damping intermediate pillar portion 14b and a plurality of outer steel plates 7a fixed on the other damping intermediate pillar portion 14a. The inner and outer steel plates are arranged alternately in a single or a plurality of layers, between which a viscoelastic member 15 is held to make up a viscoelastic damper 17. The coupling end surfaces of the intermediate pillar portions 14a, 14b directed vertically are fixed on the upper and lower floor beams 3a, 3b. Further, one or both sides of each of the damping intermediate pillar portions 14a, 14b (i.e. the coupling members 13a, 13b) and the upper and lower floor beams 3a, 3b are coupled to each other by knee braces 19.
摘要翻译：公开了一种阻尼中间柱，其通过加强阻尼中间柱和上梁和下梁之间的接合而能够表现出抵抗强烈地震的水平力的足够阻力。用于建筑物或由支柱1和梁3构成的结构的阻尼中间柱14被分成H形钢的上下阻尼中间柱部分14a，14b，并且包括多个内钢板7 b固定在阻尼中间柱部分14b上，多个外部钢板7a固定在另一个阻尼中间柱部分14a上。内钢板和外钢板交替地布置成一个或多个层，在其间保持粘弹性构件15以构成粘弹性阻尼器17。垂直定向的中间柱部分14a，14b的连接端面固定在上下地板梁3a，3b上。此外，每个阻尼中间柱部分14a，14b（即，联接构件13a，13b）和上部和下部地板梁3a，3b的一侧或两侧通过膝盖支架彼此联接 19。

84. 发明申请

US20060133155A1 Nonvolatile semiconductor memory device and a method of erasing data thereof 审中-公开
标题翻译：非易失性半导体存储器件及其数据的擦除方法
公开(公告)号：US20060133155A1
公开(公告)日：2006-06-22
申请号：US11293376
申请日：2005-12-05
申请人： Norihiro Fujita , Hiroshi Nakamura
发明人： Norihiro Fujita , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3445
摘要： A nonvolatile semiconductor memory device comprises memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, before erasing data of all of said memory cells in the selected memory block in a plurality of said memory blocks, preprogram is performed to shift all threshold voltages of all of said memory cells in said selected memory blocks to positive.
摘要翻译：非易失性半导体存储器件包括由多个存储单元构成的存储单元阵列，所述存储单元阵列在擦除多个所述存储器块中所选择的存储器块中的所有存储单元的数据之前，布置电可重写存储单元，将所选择的存储器块中的所有存储单元的所有阈值电压移位为正。

85. 发明申请

US20060114729A1 Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US20060114729A1
公开(公告)日：2006-06-01
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

86. 发明申请

US20060067044A1 Supporting apparatus for electronic device 审中-公开
标题翻译：电子设备配套设备
公开(公告)号：US20060067044A1
公开(公告)日：2006-03-30
申请号：US11236009
申请日：2005-09-27
申请人： Mitsuhiro Yoshida , Hiroshi Nakamura , Shinichi Kido
发明人： Mitsuhiro Yoshida , Hiroshi Nakamura , Shinichi Kido
IPC分类号： G06F1/16
CPC分类号： G06F1/1632
摘要： A supporting apparatus includes a connector, a first hook portion and a second hook portion. The connector is connected to a signal terminal provided at a bottom portion of a portable computer that is chosen from a plurality of electronic devices having different sizes which are dimensions measured from the bottom portions to outer peripheral edges of the portable computes. The first hook portion is provided with respect to the connector in a position corresponding to that of the outer peripheral edge of one of the portable computers. The second hook portion is provided with respect to the connector in a position corresponding to the outer peripheral edge of another of the portable computers.
摘要翻译：支撑装置包括连接器，第一钩部和第二钩部。连接器连接到设置在便携式计算机的底部的信号端子，该信号端子是从具有不同尺寸的多个电子设备中选择的，这些电子设备是从便携式计算机的底部到外围边缘测量的尺寸。第一钩部相对于连接器设置在与便携式计算机之一的外围边缘相对应的位置。第二钩部相对于连接器设置在与另一个便携式计算机的外围边缘对应的位置。

87. 发明授权

US07016228B2 Semiconductor storage device having page copying function 有权
公开(公告)号：US07016228B2
公开(公告)日：2006-03-21
申请号：US10699398
申请日：2003-10-31
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/105 , G11C7/1006 , G11C7/1021 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/3431 , H01L27/115
摘要： Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

88. 发明授权

US07009878B2 Data reprogramming/retrieval circuit for temporarily storing programmed/retrieved data for caching and multilevel logical functions in an EEPROM 有权
标题翻译：数据重新编程/检索电路，用于临时存储用于EEPROM中的缓存和多级逻辑功能的编程/检索数据
公开(公告)号：US07009878B2
公开(公告)日：2006-03-07
申请号：US10664977
申请日：2003-09-22
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列并且彼此传送数据的第一锁存器和第二锁存器。一个控制器控制重新编程和检索电路的数据重新编程操作和数据检索操作从存储单元阵列。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器在存储单元之一中存储两位四电平数据来执行二位四电平数据的高位和低位的重新编程和检索在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

89. 发明申请

US20060044288A1 Multi-functional electronic device utilizing a stylus pen 审中-公开
标题翻译：使用手写笔的多功能电子设备
公开(公告)号：US20060044288A1
公开(公告)日：2006-03-02
申请号：US10871080
申请日：2004-06-18
申请人： Hiroshi Nakamura , Toshiyuki Tanaka
发明人： Hiroshi Nakamura , Toshiyuki Tanaka
IPC分类号： G09G5/00
CPC分类号： G06F3/03545 , G06F1/1626 , G06F1/1628 , G06F1/166 , G06F1/169 , G06F3/0338 , G06F2200/1614 , G06F2200/1632
摘要： According to one embodiment of the invention, an electronic device, such as a tablet PC for example, is designed with a housing and a cover configured for attachment to the housing. The housing includes a front panel and a back panel having a base unit with a recess to receive a stylus pen to operate as a leg to maintain the housing in an upright position. Alternatively, the housing may include a control button to receive a stylus pen so that the combination operates as an input device similar to a joystick.
摘要翻译：根据本发明的一个实施例，例如诸如平板电脑的电子设备被设计成具有被配置为附接到壳体的壳体和盖子。壳体包括前面板和后面板，后面板具有带有凹部的基座单元，用于接收触控笔以作为腿部维持壳体处于直立位置。或者，壳体可以包括用于接收触针笔的控制按钮，使得该组合作为类似于操纵杆的输入装置操作。

90. 发明申请

US20060022745A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20060022745A1
公开(公告)日：2006-02-02
申请号：US11184918
申请日：2005-07-20
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G05F1/10
CPC分类号： G05F3/247
摘要： A semiconductor integrated circuit device includes: a circuit node to be set at a certain operating voltage; and a voltage stabilizing capacitor connected to the circuit node, wherein the voltage stabilizing capacitor is formed of at least two MOS capacitors coupled in parallel with each other, which show different capacitance changes from each other in accordance with an applied voltage change.
摘要翻译：一种半导体集成电路器件，包括：要设置在一定工作电压的电路节点; 以及连接到所述电路节点的稳压电容器，其中所述稳压电容器由至少两个彼此并联耦合的MOS电容器形成，所述至少两个MOS电容器根据施加的电压变化显示彼此不同的电容变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式