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81. 发明申请

US20070120197A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WTH A STRESSED FILM 有权
标题翻译：用于增强NMOSFET和PMOSFET性能的方法和结构WTH A受压膜
公开(公告)号：US20070120197A1
公开(公告)日：2007-05-31
申请号：US11561047
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

82. 发明授权

US07183613B1 Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film 有权
标题翻译：用应力膜增强NMOSFET和PMOSFET性能的方法和结构
公开(公告)号：US07183613B1
公开(公告)日：2007-02-27
申请号：US11164224
申请日：2005-11-15
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L27/01
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极堆叠每个都由在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

83. 发明申请

US20060237791A1 Ultra thin body fully-depleted SOI MOSFETs 有权
标题翻译：超薄体全耗尽SOI MOSFET
公开(公告)号：US20060237791A1
公开(公告)日：2006-10-26
申请号：US11473757
申请日：2006-06-23
申请人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
发明人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772
摘要： A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.
摘要翻译：提供了一种制造超薄体全耗尽SOI MOSFET的方法，其中SOI厚度随栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

84. 发明申请

US20060022270A1 ULTRA-THIN BODY SUPER-STEEP RETROGRADE WELL (SSRW) FET DEVICES 有权
标题翻译：超声波超声波超声波（SSRW）FET器件
公开(公告)号：US20060022270A1
公开(公告)日：2006-02-02
申请号：US10710736
申请日：2004-07-30
申请人： Diane Boyd , Judson Holt , MeiKei Ieong , Renee Mo , Zhibin Ren , Ghavam Shahidi
发明人： Diane Boyd , Judson Holt , MeiKei Ieong , Renee Mo , Zhibin Ren , Ghavam Shahidi
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

85. 发明申请

US20060001095A1 ULTRA THIN BODY FULLY-DEPLETED SOI MOSFETS 失效
标题翻译：超薄体全绝缘SOI MOSFET
公开(公告)号：US20060001095A1
公开(公告)日：2006-01-05
申请号：US10710273
申请日：2004-06-30
申请人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
发明人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772
摘要： A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.
摘要翻译：提供了一种制造超薄体全耗尽SOI SOI的方法，其中SOI厚度随着栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

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