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81. 发明专利

JP2006343999A FILE MANAGEMENT SYSTEM 审中-公开
公开(公告)号：JP2006343999A
公开(公告)日：2006-12-21
申请号：JP2005168982
申请日：2005-06-09
申请人： HITACHI LTD
发明人： YAO KOICHI , TANAKA HITOSHI , NAKAMOTO MAKOTO
IPC分类号： G06F12/00
摘要： PROBLEM TO BE SOLVED: To provide a file management system and method enabling a user to operate files without being aware of the storage locations of the files. SOLUTION: Physical storage locations and logical storage locations are separately managed as directory structures and hierarchical structures, respectively. When files are displayed, the storage locations of the files are determined from the reference pathes and the relative buses of the files and the files are obtained from the storage locations. To change the storage locations of the files, it is verified whether or not the requirements for changing the storage location are met for each reference path ID, and the reference path for which the storage location is to be changed is determined. Based on the reference path before the change and the reference path after the change, the storage location of the file before the change and the storage location of the file after the change are determined, and the file is moved from the storage location of the file before the change to the storage location of the file after the change. Also, the reference path for which the storage location is changed is changed into a reference path for the storage location after the change. COPYRIGHT: (C)2007,JPO&INPIT

82. 发明专利

JP2003110030A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003110030A
公开(公告)日：2003-04-11
申请号：JP2002180774
申请日：2002-06-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： H01L27/04 , G05F3/26 , G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To stabilize output voltage of an internal voltage generating circuit. SOLUTION: A MOS capacitor having a negative threshold voltage is formed and the capacitor is connected to the output of the internal voltage generating circuit. Since the MOS capacitor has a negative voltage, a current collecting capacity is stabilized without depending upon the magnitude of applied voltage, and the capacitor can be readily formed in a manner consistent with the producing process of a MOSFET.

83. 发明专利

JP2001006361A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001006361A
公开(公告)日：2001-01-12
申请号：JP17662999
申请日：1999-06-23
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA HITOSHI
IPC分类号： G11C11/407 , G05F1/618 , G11C5/14 , G11C11/4074 , H02M3/07 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To simplify circuits of a device and to reduce the power consumption of the device by constituting a voltage generating circuit in a chip with two sets of differential circuits driving output transistors of a push-pull output circuit while comparing output voltage of the push-pull output circuit with a reference voltages and preventing a through-current from flowing through the push-pull output circuit while making the differential circuits have an offset. SOLUTION: An offset is set in differential circuits N-AMP, P-AMP. Namely, when an output voltage VMP is lower than a reference voltage HVDL, an output current making the gate voltage N1 of an output MOSFET-M1 a low level is formed from the differential circuit N-AMP to make the output MOSFET-M1 to be in an on-state and a current is supplied to an output node 10 to make the output voltage VMP high. Then, the P channel type output MOSFET-M1 becomes an off-state by the offset. Moreover, when the output voltage VMP is higher than the reference voltage HVDL, an output current making a gate voltage N7 a high level is formed from the differential circuit P-AMP.

84. 发明专利

JP2000353785A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000353785A
公开(公告)日：2000-12-19
申请号：JP2000139396
申请日：2000-05-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To feed a stable reference voltage to a drive circuit. SOLUTION: A reference voltage generating circuit, a wiring 109b which connects the reference voltage generating circuit to a drive circuit that outputs the inner voltage receiving a reference voltage, wirings 109a and 109c, a shielding wire provided to a lower layer 108 which interpose an insulating layer between them are provided, by which both the shielding wires are kept at a ground potential. Or a third shielding wire 106 and a fourth shielding wire 109 are provided to a second and a third wiring layer which are different from a first wiring layer, composed of a wiring 108b and two shielding wires 108a and 108c. By this setup, a semiconductor device can be protected against influence of noises due to other circuits inside a semiconductor chip or a coupling capacitor, so that a reference voltage can be supplied stably to a drive circuit.

85. 发明专利

JP2000075941A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2000075941A
公开(公告)日：2000-03-14
申请号：JP24471698
申请日：1998-08-31
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , Texas Instr Inc , テキサスインスツルメンツインコーポレイテツド , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TANAKA HITOSHI , EBIHARA TAKASHI , IWASAKI HIDEAKI
IPC分类号： G11C11/413 , G05F1/56 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To make obtainable a desired voltage at a load terminal even when wiring resistance is large by providing a step-down circuit whose output voltage rises as a load current increases.
SOLUTION: The step-down circuit VREG has double-end type differential amplifiers (M1 to M5) and circuits (M6 to M9) which convert their two outputs into single-end push-pull outputs. As a current IL flows to a load, a current kIL which is proportional to the IL flows to an output transistor M10 and an M12 having its gate and source connected in common. Since M13 to M15 are connected in a current-mirror type, currents nIL and mIL, which are proportional to the IL, flow thereto. Since the M14 is connected to the output of the outputs of the push-pull converting circuits, when the IL increases, its node potential is lowered. Consequently, the gate-source voltage of the M10 rises and the level of the output out rises.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：即使通过提供输出电压随负载电流增加而升高的降压电路，即使在布线电阻较大时，也能够在负载端子获得期望的电压。解决方案：降压电路VREG具有双端型差分放大器（M1至M5）和电路（M6至M9），可将其两路输出转换为单端推挽输出。当电流IL流向负载时，与IL成比例的电流kIL流向输出晶体管M10，并且其门和源的M12共同连接。由于M13至M15以电流镜型连接，所以与IL成比例的电流nIL和mIL流向其。由于M14连接到推挽转换电路的输出的输出，所以当IL增加时，其节点电位降低。因此，M10的栅源电压上升，输出电平上升。

86. 发明专利

JP2000057764A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000057764A
公开(公告)日：2000-02-25
申请号：JP22132198
申请日：1998-08-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： EBIHARA TAKASHI , TANAKA HITOSHI
IPC分类号： G11C11/419 , G11C11/407 , G11C11/409
摘要： PROBLEM TO BE SOLVED: To correct a step-down power supply line to normal potential even when the step-down power supply line is excessively charged by overdrive operation by making different the size of at least one of transistors for composing first and second differential amplifies between the first and second differential amplifiers. SOLUTION: When the potential of a node N2 of a differential amplifier PL rises, current that flows to a negative-side input transistor in the differential amplifier PL is increased, thus increasing the current of a transistor Q6, and pulling out a VDH. A reference voltage is set to VLH/2, and feedback from the VDH is also set to the half of the VDH by voltage divided by a resistor, and is inputted to the gate of the input transistor in the differential amplifier PL, thus the driving capability is secured, and a stabilized operation can be obtained. A p-MOS is used for a transistor for pulling out, an n-MOS is used for a transistor for charge driving, and source follower connection is made, thus decreasing a loop gain, increasing a phase margin, and hence overshooting is prevented.

87. 发明专利

JPH11288593A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11288593A
公开(公告)日：1999-10-19
申请号：JP4266599
申请日：1999-02-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KUME EIJI , TANAKA HITOSHI , NAKAGOME YOSHINOBU , KAWAJIRI YOSHIKI , ITO KIYOO
IPC分类号： G11C11/419 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To lower only signal amplitudes of principal circuits by preliminarily driving the voltage between the gate and the source (drain) or the voltage between the drain and the source of a MOS-FET dynamically or statically with a large voltage value sufficiently larger than the threshold value of the MOS-FET. SOLUTION: When a P1P is made to be from a VDL (1.0 V) to a VSS (0 V) and a P1N is made to be from the VSS (0 V) to the VDL (1.0 V), transistors QP, QN for driving sense amplifier are turned ON and sense amplifier driving lines CSP and CSN are respectively changed from a HVC (0.5 V) to the VDL (1.0 V), from the HVC (0.5 V) to the VSS (0 V). At this time, since a sense amplifier uses transistors Q1', Q2', Q3, Q4' whose threshold voltages are low, the voltage between the gate and the source (drain) is sufficiently larger than the threshold voltage and transistors of the sense amplifier are sufficiently turned ON to sufficiently amplify the signal voltage of data lines. Then, charging and discharging speeds of the data lines become faster a little.

88. 发明专利

JPH11288591A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11288591A
公开(公告)日：1999-10-19
申请号：JP2964899
申请日：1999-02-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/413 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To stabilize the operation of a voltage limiter circuit by including a MOS capacitor whose threshold voltage is negative in an internal voltage generating circuit generating internal voltages by receiving an operating power source voltage. SOLUTION: In drive circuits 7a, 7b, when wirings of outputs of the circuits intersect a wiring 12a, a feedback circuit is generated via the parasitic capacitance CC3 between wirings and operations of the circuits becomes unstable. In order to prevent this unstableness, the gain of a loop is made to be sufficiently small by inserting capacitors CR1 , CR2 whose capacitances are sufficiently larger than parastic capacitances CC1 to CC3 . Capacitors to be used in here are formed between gates and a substrate surface across a gate insulating film and large capacitances can be obtained with relatively small areas by using a thin gate insulating film as a capacitor insulating film. Since there are wells under the gates, the threshold voltage of the capacitors is negative and capacitances of the capacitors becomes roughly constant as long as a voltage of one direction is applied on them so that sides of gates become positive.

89. 发明专利

JPH11288586A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11288586A
公开(公告)日：1999-10-19
申请号：JP2964799
申请日：1999-02-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/413 , G05F3/24 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To suppress the level of noise to be generated in a device by arranging a voltage limiter circuit and the load circuit of a pulse generating circuit or the like closely to make impedances of wirings between these circuits small. SOLUTION: A reference voltage generating circuit 6 and drive circuits 7a to 7d are separated and the reference voltage generating circuit 6 and the drive circuits are respectively arranged in the vicinity of a bonding pad for inputting ground potentials and in the vicinity of respective load circuits. As a result, a grounding wiring 8 from the pad till the circuit 6 and internal power source wirings 11a to 11d from respective driving circuits till respective load circuits are shortened and their impedances become small. Thus, noise being on the wiring 8 is reduced and the ground level of the circuit 6 is stabilized and a constant reference voltage is obtained. Moreover, the short wiring 8 dedicated for the circuit 6 and wirings 9a to 9d for other circuits are provided is provided as a grounding wiring method.

90. 发明专利

JPH1117019A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING WIRING PROGRAMMING ELEMENT USED FOR THE DEVICE 失效
公开(公告)号：JPH1117019A
公开(公告)日：1999-01-22
申请号：JP18063397
申请日：1997-06-20
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： SEKIGUCHI TOMONORI , KIMURA SHINICHIRO , TANAKA HITOSHI , NODA HIROMASA , AOKI MASAKAZU , KAWAMOTO HIROSHI
IPC分类号： H01L21/82 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/112
摘要： PROBLEM TO BE SOLVED: To make it possible to form an element in microscopic size by a method wherein a wiring programming element, to be selectively cut, is composed of the top wiring layer, and after formation of the surface of the first insulating film, the second insulating film, covering the cutting surface and the aperture part of the programming wiring part, is formed. SOLUTION: The top layer of a metal wiring layer M3, which constitutes a wiring programming element to be selectively cut corresponding to the result of the electric test on an electronic circuit, is formed on an interlayer insulating film INS4. Then, the surface of the first insulating film INS5, excluding the fixed wiring of the electronic circuit provided on the interlayer insulating film IND4 is formed. A program cutting part HP and the surface of a pad part, is formed. Subsequently, resist is applied on the first insulating film INS5, and an aperture is provided on the resist on the upper part of the wiring programming element to be cut by EB(electron beam) lithography. Lastyl, the first insulating film INS5 is etched using the resist as a mask, and the second insulating film INS6 is deposited.

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