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    • 82. 发明申请
    • Method and apparatus for inspecting defects of semiconductor device
    • 用于检查半导体器件缺陷的方法和装置
    • US20070036421A1
    • 2007-02-15
    • US11500979
    • 2006-08-09
    • Tadanobu TobaShuji KikuchiYuichi SakuraiWen Li
    • Tadanobu TobaShuji KikuchiYuichi SakuraiWen Li
    • G06K9/00
    • G06T7/0004G06T2207/30148
    • When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.
    • 当半导体装置的检查装置重复执行规定区域数据的计算时,例如用于检测缺陷的图像处理,命令,数据加载,计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外,当通过大容量图像处理系统执行并行计算以处理微小图像时,需要许多处理器,导致成本增加。 为了解决上述问题,在本发明中,半导体装置的检查装置包括数据存储器,该数据存储器包括能够同时读写的访问部分,多个数值计算单元,连接器 数据存储器和数值计算单元,用于共同控制多个数值计算单元的处理内容的控制器,用于连接数值计算单元和控制器的另一连接器,以及用于控制数值计算之间的数据传送的数据传输控制器 单位。
    • 89. 发明授权
    • Phase detector and method having hysteresis characteristics
    • 相位检测器和方法具有滞后特性
    • US07119583B2
    • 2006-10-10
    • US10816178
    • 2004-03-31
    • Gary JohnsonWen Li
    • Gary JohnsonWen Li
    • G01R25/00
    • H03D13/004
    • A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.
    • 如果反馈时钟信号超过第一次引导参考时钟信号,则相位检测器产生第一输出信号。 如果反馈时钟信号比第二次滞后于参考时钟信号,则相位检测器产生第二输出信号。 如果反馈时钟信号通过小于第一次引导参考时钟信号或者将参考时钟信号滞后小于第二次,则不会产生输出信号。 相位检测器可以用在延迟锁定环路中,其中第一和第二输出信号通过相应的第一和第二延迟增量来增加或减小参考时钟信号的延迟。 在这种情况下,第一和第二延迟增量中的每个应该小于第一次和第二次的和。
    • 90. 发明申请
    • System and method for performing decimal division
    • US20060179102A1
    • 2006-08-10
    • US11055221
    • 2005-02-10
    • Steven CarloughPaulomi KadakiaWen LiEric Schwarz
    • Steven CarloughPaulomi KadakiaWen LiEric Schwarz
    • G06F7/52
    • G06F7/4917G06F2207/5352
    • A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.