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81. 发明申请

US20100164603A1 Programmable fuse and anti-fuse elements and methods of changing conduction states of same 有权
标题翻译：可编程保险丝和反熔丝元件以及改变导通状态的方法
公开(公告)号：US20100164603A1
公开(公告)日：2010-07-01
申请号：US12319104
申请日：2008-12-30
申请人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
发明人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
IPC分类号： H01H37/76 , H01L29/00
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.
摘要翻译：可编程抗熔丝元件包括衬底（224），衬底中的N阱（426），在N阱上的电绝缘层（427）以及电绝缘层上的栅电极（430）。栅电极具有n型掺杂，使得N阱能够在其边界内基本上包含在可编程反熔丝元件的编程事件之后产生的电流。在相同或另一个实施例中，两次可编程熔丝元件（100）包括金属栅极熔丝（110）和氧化物反熔丝（120），例如刚刚描述的可编程反熔丝元件。

82. 发明授权

US07691718B2 Dual layer hard mask for block salicide poly resistor (BSR) patterning 失效
标题翻译：双层硬掩模用于块状硅化物电阻（BSR）图案化
公开(公告)号：US07691718B2
公开(公告)日：2010-04-06
申请号：US12005944
申请日：2007-12-27
申请人： Joodong Park , Chia-Hong Jan , Paul Reese
发明人： Joodong Park , Chia-Hong Jan , Paul Reese
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L28/24
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
摘要翻译：通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。氧化物层在衬底上。在氧化物层上形成氮化物层并进行退火。在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。使用抗蚀剂层作为图案蚀刻退火的氮化物层。去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

83. 发明授权

US07115502B2 Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process 有权
标题翻译：局部分流的结构和制造过程，以减少铜双镶嵌工艺的电迁移故障
公开(公告)号：US07115502B2
公开(公告)日：2006-10-03
申请号：US11026078
申请日：2004-12-30
申请人： Chia-Hong Jan
发明人： Chia-Hong Jan
IPC分类号： H02L21/44
CPC分类号： H01L21/76886 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure to reduce electromigration failure of semiconductor interconnects. In various embodiments, the area around a via is selectively doped with metallic dopants. The method and resulting structure reduce electromigration failure without adding unnecessary, performance-degrading resistance.
摘要翻译：减少半导体互连的电迁移故障的方法和结构。在各种实施例中，通孔周围的区域被选择性地掺杂有金属掺杂剂。该方法和结果可以减少电迁移故障，而不会增加不必要的性能降低电阻。

84. 发明授权

US07071129B2 Enhancing adhesion of silicon nitride films to carbon-containing oxide films 失效
标题翻译：提高氮化硅膜对含碳氧化膜的粘附性
公开(公告)号：US07071129B2
公开(公告)日：2006-07-04
申请号：US10242086
申请日：2002-09-12
申请人： Chia-Hong Jan , Tracey Scherban , Ying Zhou , Adam Schafer , Brett Robert Schroeder
发明人： Chia-Hong Jan , Tracey Scherban , Ying Zhou , Adam Schafer , Brett Robert Schroeder
IPC分类号： H01L21/26 , H01L21/324 , H01L21/31 , H01L23/48
CPC分类号： H01L21/02126 , H01L21/0217 , H01L21/022 , H01L21/0234 , H01L21/31633 , H01L21/3185 , H01L23/53295 , H01L2924/0002 , Y10S438/964 , H01L2924/00
摘要： Adhesion between silicon nitride etch-stop layers and carbon doped oxide films may be improved by using plasma argon densification treatments of the carbon doped oxide films. The resulting surface layer of the carbon doped oxide films may be carbon-depleted and may include a relatively rough interface to improve the adhesion of deposited silicon nitride films.
摘要翻译：通过使用掺杂碳的氧化物膜的等离子体氩致密化处理可以改善氮化硅蚀刻停止层和掺碳氧化物膜之间的粘合性。得到的碳掺杂氧化物膜的表面层可以是碳贫的，并且可以包括相对粗糙的界面以改善沉积的氮化硅膜的粘附性。

85. 发明申请

US20050191411A1 Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process 有权
标题翻译：局部分流的结构和制造过程，以减少铜双镶嵌工艺的电迁移故障
公开(公告)号：US20050191411A1
公开(公告)日：2005-09-01
申请号：US11026078
申请日：2004-12-30
申请人： Chia-Hong Jan
发明人： Chia-Hong Jan
IPC分类号： H01L21/768 , H01L23/522 , B05D5/00 , B05D5/12
CPC分类号： H01L21/76886 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure to reduce electromigration failure of semiconductor interconnects. In various embodiments, the area around a via is selectively doped with metallic dopants. The method and resulting structure reduce electromigration failure without adding unnecessary, performance-degrading resistance.
摘要翻译：减少半导体互连的电迁移故障的方法和结构。在各种实施例中，通孔周围的区域被选择性地掺杂有金属掺杂剂。该方法和结果可以减少电迁移故障，而不会增加不必要的性能降低电阻。

86. 发明授权

US06777760B1 Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates 有权
标题翻译：具有凹陷的薄而厚的间隔物的装置，用于改善多晶硅栅极上的耐着雾性
公开(公告)号：US06777760B1
公开(公告)日：2004-08-17
申请号：US09477870
申请日：2000-01-05
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J Keating , Alan Myers
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

87. 发明授权

US06506652B2 Method of recessing spacers to improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅栅极上使间隔物凹陷的方法提高了耐剥落性
公开(公告)号：US06506652B2
公开(公告)日：2003-01-14
申请号：US09458357
申请日：1999-12-09
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

88. 发明授权

US06479391B2 Method for making a dual damascene interconnect using a multilayer hard mask 失效
公开(公告)号：US06479391B2
公开(公告)日：2002-11-12
申请号：US09746035
申请日：2000-12-22
申请人： Patrick Morrow , Jihperng Leu , Chia-Hong Jan
发明人： Patrick Morrow , Jihperng Leu , Chia-Hong Jan
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/31144 , H01L21/76811 , H01L21/76813
摘要： An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.

89. 发明授权

US06188117B1 Method and device for improved salicide resistance on polysilicon gates 有权
标题翻译：在多晶硅闸门上提高耐化学性的方法和装置
公开(公告)号：US06188117B1
公开(公告)日：2001-02-13
申请号：US09276477
申请日：1999-03-25
申请人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
发明人： Chia-Hong Jan , Julie A. Tsai , Simon Yang , Tahir Ghani , Kevin A. Whitehill , Steven J. Keating , Alan Myers
IPC分类号： H01L3300
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933 , H01L29/66575 , Y10S257/90
摘要： A method and device for improved polycide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
摘要翻译：一种在0.20μm以下多晶硅栅极中提高多晶硅栅极电阻的方法和装置。本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。另一实施例提供具有两个间隔堆叠的栅电极结构。最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

90. 发明授权

US06165826A Transistor with low resistance tip and method of fabrication in a CMOS process 失效
标题翻译：具有低电阻尖端的晶体管和CMOS工艺中的制造方法
公开(公告)号：US06165826A
公开(公告)日：2000-12-26
申请号：US581243
申请日：1995-12-29
申请人： Robert S. Chau , Chia-Hong Jan , Chan-Hong Chern , Leopoldo D. Yau
发明人： Robert S. Chau , Chia-Hong Jan , Chan-Hong Chern , Leopoldo D. Yau
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66613 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.
摘要翻译：一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极具有第二导电类型的半导体衬底的部分。在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。然后在凹部中形成选择性淀积的半导体材料。

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