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81. 发明申请

US20060186451A1 Memory device for storing electric charge, and method for fabricating it 审中-公开
标题翻译：用于存储电荷的存储装置及其制造方法
公开(公告)号：US20060186451A1
公开(公告)日：2006-08-24
申请号：US11363991
申请日：2006-02-28
申请人： Georg Dusberg , Andrew Graham , Franz Kreupl
发明人： Georg Dusberg , Andrew Graham , Franz Kreupl
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： G11C13/0033 , B82Y10/00 , G11C13/025 , G11C2213/16 , H01L27/10817 , H01L27/1085 , H01L27/10852 , H01L28/91 , H01L51/0048 , H01L51/0052
摘要： The present device relates to memory devices for storing electric charge having memory cells and transistors arranged spatially next to them, and relates in particular to memory devices having memory cells with a high capacitance. In the memory cells which form a memory device to which the invention relates, there is a substrate and at least one memory cell which is arranged on the substrate and includes a first electrode element, which is electrically connected to the substrate, an insulation layer, which has been applied to the first electrode element, and a second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element.
摘要翻译：本装置涉及用于存储电荷的存储装置，该电荷具有存储单元和在空间上排列的晶体管，特别涉及具有高电容的存储单元的存储器件。在形成本发明所涉及的存储器件的存储器单元中，存在一个衬底和至少一个存储单元，其被布置在衬底上，并且包括与衬底电连接的第一电极元件，绝缘层，已经施加到第一电极元件的第二电极元件和已经施加到绝缘层并且与第一电极元件电绝缘的第二电极元件。

82. 发明申请

US20060154467A1 Method for the production of a memory cell, memory cell and memory cell arrangement 审中-公开
标题翻译：用于生产存储器单元，存储单元和存储单元布置的方法
公开(公告)号：US20060154467A1
公开(公告)日：2006-07-13
申请号：US10537534
申请日：2003-11-27
申请人： Franz Hoffman , Franz Kreupl
发明人： Franz Hoffman , Franz Kreupl
IPC分类号： H01L21/20 , H01L21/44
CPC分类号： G11C13/0011 , B82Y10/00 , B82Y30/00 , G11C2213/15 , G11C2213/77 , G11C2213/79 , H01L27/2454 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/16
摘要： The invention relates to a method for the production of a memory cell, a memory cell and a memory cell arrangement. According to the inventive method for the production of a memory cell, a first electrically conductive area is formed in and/or on a substrate. A second electrically conductive area is also formed at a given distance from the first electrically conductive area such that a cavity is formed between the first and second electrically conductive areas. The first and second electrically conductive areas are configured in such a way that when a first voltage is applied to the electrically conductive areas, a structure is formed from material from at least one of said electrically conductive areas, at least partically bridging over the distance between the electrically conductive areas. When a second voltage is applied to the conductive areas, the material of the structure at least partically bridging over the distance between the electrically conductive areas recedes.
摘要翻译：本发明涉及一种用于生产存储单元，存储单元和存储单元布置的方法。根据用于制造存储单元的本发明的方法，在衬底中和/或衬底上形成第一导电区域。第二导电区域也形成在距离第一导电区域给定距离处，使得在第一和第二导电区域之间形成空腔。第一导电区域和第二导电区域被构造成使得当第一电压被施加到导电区域时，结构由至少一个所述导电区域的材料形成，至少部分地跨越在导电区域。当将第二电压施加到导电区域时，至少部分桥接在导电区域之间的距离的结构的材料后退。

83. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

84. 发明申请

US20050029654A1 IC chip with nanowires 失效
标题翻译：具有纳米线的IC芯片
公开(公告)号：US20050029654A1
公开(公告)日：2005-02-10
申请号：US10902486
申请日：2004-07-29
申请人： Hannes Mio , Franz Kreupl
发明人： Hannes Mio , Franz Kreupl
IPC分类号： G11C13/02 , G11C17/06 , H01L23/58 , H01L27/32 , H01L29/06 , H01L29/73 , H01L29/78 , H01L29/861 , H01L51/00 , H01L51/05 , H01L51/30 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/025 , G11C17/06 , G11C2213/81 , H01L23/57 , H01L27/32 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/73 , H01L29/78 , H01L29/861 , H01L51/0048 , H01L51/0052 , H01L51/0504 , H01L2924/0002 , Y10S257/91 , Y10S257/922 , H01L2924/00
摘要： Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as transistors which turn on or turn off only when a gate voltage is applied. A number of these transistors are constructed in complementary fashion and/or have insulating regions built in and serve as a dummy.
摘要翻译：位线和字线之间的PN结的纳米线的布置被布置为ROM存储单元阵列。许多纳米线具有电介质区域并且仅作为虚拟物存在。字和位线之间的连接也可以作为仅在施加栅极电压时导通或截止的晶体管存在。多个这些晶体管以互补的方式构造和/或具有内置并用作虚拟的绝缘区域。

85. 发明授权

US06777731B2 Magnetoresistive memory cell with polarity-dependent resistance 失效
标题翻译：具有极性依赖性电阻的磁阻存储单元
公开(公告)号：US06777731B2
公开(公告)日：2004-08-17
申请号：US10352730
申请日：2003-01-27
申请人： Franz Kreupl
发明人： Franz Kreupl
IPC分类号： H01L2976
CPC分类号： H01L43/08 , B82Y25/00 , G11C11/16 , H01F10/3254 , H01L27/222
摘要： A magnetoresistive tunnel element includes first and second electrodes and a tunnel barrier disposed between the two electrodes, the tunnel barrier having at least two barrier layers made of different barrier materials, the profile of a quantum mechanical barrier height within the tunnel barrier being asymmetrical and the conductivity of the tunnel element, therefore, being dependent on the polarity of a voltage Um between the two electrodes. Also provided is a magnetoresistive memory cell, a cell array of magnetoresistive memory cells, and a memory device having cell arrays.
摘要翻译：磁阻隧道元件包括第一和第二电极和设置在两个电极之间的隧道势垒，隧道势垒具有由不同阻挡材料制成的至少两个阻挡层，隧道势垒内的量子力学势垒高度的轮廓是不对称的，因此，隧道元件的导电性取决于两个电极之间的电压Um的极性。还提供了磁阻存储单元，磁阻存储单元的单元阵列以及具有单元阵列的存储器件。

86. 发明授权

US08912654B2 Semiconductor chip with integrated via 有权
标题翻译：半导体芯片集成通孔
公开(公告)号：US08912654B2
公开(公告)日：2014-12-16
申请号：US12101501
申请日：2008-04-11
申请人： Franz Kreupl , Harry Hedler
发明人： Franz Kreupl , Harry Hedler
IPC分类号： H01L23/48 , H01L23/52 , H01L21/44 , H01L21/683 , H01L21/768 , H01L25/065 , H01L23/00
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/76898 , H01L24/11 , H01L24/12 , H01L25/0657 , H01L2221/68372 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/13025 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/2518 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/01079 , H01L2924/14 , H01L2924/19041 , H01L2224/05552
摘要： An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.
摘要翻译：描述了具有下表面和上表面的基底的集成电路。通孔延伸在基板的上表面和下表面之间。通孔含有包含碳的导电填充材料。

87. 发明授权

US08664657B2 Electrical circuit with a nanostructure and method for producing a contact connection of a nanostructure 失效
标题翻译：具有纳米结构的电路和用于产生纳米结构的接触连接的方法
公开(公告)号：US08664657B2
公开(公告)日：2014-03-04
申请号：US11577070
申请日：2005-10-11
申请人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
发明人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
IPC分类号： H01L29/00 , H01L29/04 , H01L29/10
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0021
摘要： A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
摘要翻译：公开了一种电路。电路包括由基本上碳层形成的至少一个纳米结构和碳互连，其中纳米结构和碳互连彼此直接耦合。

88. 发明授权

US08624293B2 Carbon/tunneling-barrier/carbon diode 有权
标题翻译：碳/隧道势垒/碳二极管
公开(公告)号：US08624293B2
公开(公告)日：2014-01-07
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L29/66
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

89. 发明授权

US08503229B2 P-/Metal floating gate non-volatile storage element 有权
标题翻译： P- /金属浮动门非易失性存储元件
公开(公告)号：US08503229B2
公开(公告)日：2013-08-06
申请号：US13153964
申请日：2011-06-06
申请人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
发明人： Sanghyun Lee , Mohan Dunga , Masaaki Higashitani , Tuan Pham , Franz Kreupl
IPC分类号： G11C11/34 , G11C16/04 , H01L29/94 , H01L21/00 , H01L21/8238
CPC分类号： H01L21/28273 , H01L27/11524 , H01L27/11529 , H01L29/42324
摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有P- /金属浮动栅极的非易失性存储元件。浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。隧道氧化物附近的P-区域有助于提供良好的数据保留。控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。此外，擦除非易失性存储元件可能是有效的。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

90. 发明授权

US08471360B2 Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same 有权
标题翻译：具有具有减小的横截面积的碳开关材料的存储单元及其形成方法
公开(公告)号：US08471360B2
公开(公告)日：2013-06-25
申请号：US12760156
申请日：2010-04-14
申请人： Franz Kreupl , Er-Xuan Ping , Jingyan Zhang , Huiwen Xu
发明人： Franz Kreupl , Er-Xuan Ping , Jingyan Zhang , Huiwen Xu
IPC分类号： H01L29/92
CPC分类号： H01L45/149 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/1253 , H01L45/1616 , H01L45/1625 , H01L45/165 , H01L45/1691
摘要： In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了形成金属 - 绝缘体 - 金属（“MIM”）叠层的方法，所述方法包括：（1）在开口内形成具有开口的电介质材料和第一导电碳层; （2）在开口中形成间隔物; （3）在间隔件的侧壁上形成碳基开关材料; 和（4）在碳基开关材料上形成第二导电碳层。介电材料中的开口的横截面积与间隔件侧壁上的碳基开关材料的横截面积的比率至少为5.许多其它方面。

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