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81. 发明授权

US08307232B1 Power supply delivery for leakage suppression modes 有权
标题翻译：泄漏抑制模式的电源输送
公开(公告)号：US08307232B1
公开(公告)日：2012-11-06
申请号：US12887930
申请日：2010-09-22
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F1/26
CPC分类号： H04B1/1615 , H04W52/028 , Y02D70/40
摘要： A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.
摘要翻译：一种包括集成电路（IC）和IC外部的电源调节器的系统。 IC根据活动模式和较低功率模式工作，并且被配置为在低功率模式期间保持逻辑状态。电源调节器被配置为i）在活动模式期间向IC的第一引脚提供第一电压电位，以及ii）在低功率模式期间禁用第一电压电位。 IC被配置为经由第一引脚将IC的内部电源的第一反馈信号提供给电源调节器。

82. 发明申请

US20120140929A1 INTEGRATED CIRCUITS SECURE FROM INVASION AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：集成电路安全入侵及其制造方法
公开(公告)号：US20120140929A1
公开(公告)日：2012-06-07
申请号：US13139955
申请日：2009-12-29
申请人： Lawrence T. Clark , David R. Allee
发明人： Lawrence T. Clark , David R. Allee
IPC分类号： H01L23/60 , H01L29/786 , G09C1/00 , H01L21/50
CPC分类号： H01L23/3121 , G06F21/79 , G06F21/87 , H01L21/56 , H01L23/13 , H01L23/49833 , H01L23/57 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要： An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
摘要翻译：本文公开了一种防止侵入和相关方法的集成电路装置。本文还公开了其它实施例。

83. 发明申请

US20120063189A1 LONGEST PREFIX MATCH INTERNET PROTOCOL CONTENT ADDRESSABLE MEMORIES AND RELATED METHODS 有权
标题翻译：最大的前缀匹配互联网协议内容可寻址记忆及相关方法
公开(公告)号：US20120063189A1
公开(公告)日：2012-03-15
申请号：US13321309
申请日：2010-05-26
申请人： Satendra Kumar Maurya , Lawrence T. Clark
发明人： Satendra Kumar Maurya , Lawrence T. Clark
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G06F7/74 , G06F2213/0038 , G11C15/00 , G11C15/04 , H04L45/7457 , H04L45/748
摘要： Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.
摘要翻译：本文描述了用于因特网协议设备和操作的内容可寻址存储器的实施例。本文还公开了其它实例和相关方法。

84. 发明授权

US08122317B1 Two-dimensional parity technique to facilitate error detection and correction in memory arrays 有权
标题翻译：二维奇偶校验技术，便于存储器阵列中的错误检测和校正
公开(公告)号：US08122317B1
公开(公告)日：2012-02-21
申请号：US12163640
申请日：2008-06-27
申请人： Lawrence T. Clark , Karl C. Mohr
发明人： Lawrence T. Clark , Karl C. Mohr
IPC分类号： H03M13/00
CPC分类号： H03M13/2909 , G06F11/1012
摘要： The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in columns. A row check bit is provided for each row bundle in each super bundle. Each row check bit provides a parity bit that is derived from the k bits of the corresponding row bundle. A column check bit is provided for each column in each super bundle. Each column check bit provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle.
摘要翻译：本发明涉及用于存储在一个或多个存储器阵列中的数据的二维奇偶校验技术，每个存储器阵列具有不同的行和列的单元。超级捆绑中的一行位称为行捆绑。超级捆绑包包括多行行束，并且超级捆绑中的每个行束中的相应位在列中对齐。每个超级捆绑包中的每个行捆绑包都提供行检查位。每行检查位提供从相应行束的k位导出的奇偶校验位。每个超级包中的每列都提供列校验位。每个列校验位提供从超级组中相应列中的每个位导出的奇偶校验位。

85. 发明授权

US07920409B1 SRAM cell with intrinsically high stability and low leakage 有权
标题翻译：具有本质上高稳定性和低泄漏性的SRAM单元
公开(公告)号：US07920409B1
公开(公告)日：2011-04-05
申请号：US11758568
申请日：2007-06-05
申请人： Lawrence T. Clark , Sayeed Ahmed Badrudduza
发明人： Lawrence T. Clark , Sayeed Ahmed Badrudduza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A Static Random Access Memory (SRAM) cell having high stability and low leakage is provided. The SRAM cell includes a pair of cross-coupled inverters providing differential storage of a data bit. Power to the SRAM cell is provided by a read word line (RWL) signal, which is also referred to herein as a read control signal. During read operations, the RWL signal is pulled to a voltage level that forces the SRAM cell to a full-voltage state. During standby, the RWL signal is pulled to a voltage level that forces the SRAM cell to a voltage collapsed state in order to reduce leakage current, or leakage power, of the SRAM cell. A read-transistor providing access to the bit stored by the SRAM cell is coupled to the SRAM cell via a gate of the read transistor, thereby decoupling the stability of the SRAM cell from the read operation.
摘要翻译：提供了具有高稳定性和低泄漏的静态随机存取存储器（SRAM）单元。 SRAM单元包括一对交叉耦合的反相器，提供数据位的差分存储。 SRAM单元的电源由读取字线（RWL）信号提供，读取字线（RWL）信号在本文中也称为读取控制信号。在读取操作期间，RWL信号被拉到一个电压电平，迫使SRAM单元达到全电压状态。在待机期间，RWL信号被拉至电压电平，迫使SRAM单元处于电压合拢状态，以便降低SRAM单元的漏电流或泄漏功率。提供对SRAM单元存储的位的访问的读晶体管经由读晶体管的栅极耦合到SRAM单元，从而将SRAM单元的稳定性与读操作分离。

86. 发明申请

US20100269022A1 Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms 有权
标题翻译：具有错误检测和校正机制的双冗余寄存器文件的电路和方法
公开(公告)号：US20100269022A1
公开(公告)日：2010-10-21
申请号：US12626488
申请日：2009-11-25
申请人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
发明人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
摘要翻译：本文描述了具有错误检测和校正机制的双重冗余寄存器文件的电路和方法的实施例。本文还描述了其它实施例和相关示例。

87. 发明申请

US20100269018A1 Method for preventing IP address cheating in dynamica address allocation 有权
标题翻译：在动态地址分配中防止IP地址欺骗的方法
公开(公告)号：US20100269018A1
公开(公告)日：2010-10-21
申请号：US12626479
申请日：2009-11-25
申请人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao
发明人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao
IPC分类号： H03M13/45 , G06F11/10
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.
摘要翻译：本文描述了用于检测高速缓冲存储器中的软错误的电路的电路和方法的实施例。本文还描述了其它实施例和相关方法和示例。

88. 发明授权

US07805625B1 Power supply delivery for leakage suppression modes 有权
标题翻译：泄漏抑制模式的电源输送
公开(公告)号：US07805625B1
公开(公告)日：2010-09-28
申请号：US12284524
申请日：2008-09-23
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F1/30
CPC分类号： H04B1/1615 , H04W52/028 , Y02D70/40
摘要： A method includes providing power to on-die combinatorial circuitry of an integrated circuit (IC) from an external power supply regulator during an active mode of the IC. A state of the on-die combinatorial circuitry of the IC is moved into on-die storage of the IC. Power to the on-die combinational circuitry is disabled during a low power mode of the IC by disrupting power supplied from the external power supply regulator to the IC. A power feedback signal from an internal portion of the IC is provided to the external power supply regulator.
摘要翻译：一种方法包括在IC的有源模式期间从外部电源调节器向集成电路（IC）的片上组合电路供电。 IC的片上组合电路的状态被移动到IC的片上存储器中。通过中断从外部电源调节器提供给IC的电源，在IC的低功耗模式下禁止对芯片组合电路的电源。来自IC内部的功率反馈信号被提供给外部电源调节器。

89. 发明授权

US07541832B1 Low power, race free programmable logic arrays 失效
标题翻译：低功耗，无竞争的可编程逻辑阵列
公开(公告)号：US07541832B1
公开(公告)日：2009-06-02
申请号：US11742060
申请日：2007-04-30
申请人： Lawrence T. Clark , Giby Samson
发明人： Lawrence T. Clark , Giby Samson
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： The present invention provides a PLA architecture where the AND plane is implemented with NAND logic. The OR plane may be implemented with various logic, but in one embodiment, the OR plane is implemented with NOR logic. The AND plane may have multiple sequential stages providing hierarchical NAND logic. The NAND logic may be broken into a hierarchy of NAND logic blocks. Each NAND logic block may include one or more series-connected NAND transistor stacks. Each transistor in the transistor stack may receive an input signal representing the product of a PLA clock signal and either a direct PLA input or the complement thereof. As such, the PLA clock is inherently integrated with the input signals that drive the various transistors of the NAND transistor stacks.
摘要翻译：本发明提供了一种PLA架构，其中AND平面用NAND逻辑实现。 OR平面可以用各种逻辑来实现，但是在一个实施例中，OR平面用NOR逻辑实现。 AND平面可以具有提供分级NAND逻辑的多个连续级。 NAND逻辑可以被分解成NAND逻辑块的层级。每个NAND逻辑块可以包括一个或多个串联连接的NAND晶体管堆叠。晶体管堆叠中的每个晶体管可以接收表示PLA时钟信号和直接PLA输入或其互补的乘积的输入信号。因此，PLA时钟固有地与驱动NAND晶体管堆叠的各种晶体管的输入信号集成。

90. 发明授权

US07010706B2 Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential 失效
标题翻译：具有第一电路的设备，其在第一操作模式下向第二电路提供功率电势，否则去耦电源电位
公开(公告)号：US07010706B2
公开(公告)日：2006-03-07
申请号：US09834408
申请日：2001-04-13
申请人： Lawrence T. Clark , Neil F. Deutscher , Eric J. Hoffman
发明人： Lawrence T. Clark , Neil F. Deutscher , Eric J. Hoffman
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G11C5/14 , G11C5/147
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
摘要翻译：简而言之，根据本发明的一个实施例，集成电路具有电压调节器，其用于在逻辑电路与电源电位分离的同时向存储器电路提供电源电位。

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