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81. 发明授权

US07732872B2 Integration scheme for multiple metal gate work function structures 失效
标题翻译：多金属门功能结构的集成方案
公开(公告)号：US07732872B2
公开(公告)日：2010-06-08
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

82. 发明申请

US20100109049A1 PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE 有权
标题翻译：图形应变半导体衬底和器件
公开(公告)号：US20100109049A1
公开(公告)日：2010-05-06
申请号：US12686040
申请日：2010-01-12
申请人： Kangguo CHENG , Ramachandra Divakaruni
发明人： Kangguo CHENG , Ramachandra Divakaruni
IPC分类号： H01L29/12
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： A device that includes a pattern of strained material and relaxed material on a substrate, a strained device in the strained material, and a non-strained device in the relaxed material. The strained material may be silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. Carbon-doped silicon or germanium-doped silicon may be used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
摘要翻译：包括基材上的应变材料和松弛材料的图案的装置，应变材料中的应变装置和松弛材料中的非应变装置。应变材料可以是处于拉伸或压缩状态的硅（Si），并且松弛材料是Si处于正常状态。在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，并且晶格常数/结构与衬底失配。在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。可以使用碳掺杂硅或锗掺杂硅来形成应变材料。该结构包括具有图案化的应变和非应变材料的多层基底。

83. 发明授权

US07488642B2 Process for forming a buried plate 有权
标题翻译：掩埋板的形成工艺
公开(公告)号：US07488642B2
公开(公告)日：2009-02-10
申请号：US11715751
申请日：2007-03-08
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/945
摘要： A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is a single-crystal semiconductor region of a substrate is etched to form a trench elongated in a direction extending downwardly from a major surface of the substrate. A dopant source layer is formed to overlie a lower portion of the trench sidewall but not an upper portion of the trench sidewall. A layer consisting essentially of semiconductor material is epitaxially grown onto a single-crystal semiconductor region exposed at the upper portion of the trench sidewall above the dopant source layer. Through annealing, a dopant is then driven from the dopant source layer into the single-crystal semiconductor material of the substrate adjacent to the lower portion to form a buried plate. Then, the dopant source layer is removed and an isolation collar is formed along at least a part of the upper portion.
摘要翻译：提供了一种在半导体衬底中制造掩埋板区域的方法。根据这种方法，沟槽是衬底的单晶半导体区域被蚀刻以形成在从衬底的主表面向下延伸的方向上延伸的沟槽。掺杂剂源层形成为覆盖在沟槽侧壁的下部，而不是沟槽侧壁的上部。基本上由半导体材料组成的层被外延生长到暴露在掺杂剂源层上方的沟槽侧壁上部的单晶半导体区域上。通过退火，然后将掺杂剂从掺杂剂源层驱动到与下部相邻的衬底的单晶半导体材料中以形成掩埋板。然后，去除掺杂剂源层，沿着上部的至少一部分形成隔离环。

84. 发明申请

US20080272398A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 有权
标题翻译：用于半导体器件的导电间隔件和形成方法
公开(公告)号：US20080272398A1
公开(公告)日：2008-11-06
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

85. 发明申请

US20080261128A1 Methods and structures for protecting one area while processing another area on a chip 有权
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US20080261128A1
公开(公告)日：2008-10-23
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03F7/004 , G03F7/20
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

86. 发明授权

US07439149B1 Structure and method for forming SOI trench memory with single-sided strap 失效
标题翻译：用单面带形成SOI沟槽存储器的结构和方法
公开(公告)号：US07439149B1
公开(公告)日：2008-10-21
申请号：US11861704
申请日：2007-09-26
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

87. 发明申请

US20080191320A1 TRENCH WIDENING WITHOUT MERGING 有权
标题翻译：没有合并的TRENCH扩大
公开(公告)号：US20080191320A1
公开(公告)日：2008-08-14
申请号：US12103000
申请日：2008-04-15
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L29/04
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体结构。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

88. 发明申请

US20080166857A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20080166857A1
公开(公告)日：2008-07-10
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

89. 发明授权

US07384829B2 Patterned strained semiconductor substrate and device 有权
标题翻译：图形应变半导体衬底和器件
公开(公告)号：US07384829B2
公开(公告)日：2008-06-10
申请号：US10710608
申请日：2004-07-23
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
摘要翻译：一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。该结构包括具有图案化的应变和非应变材料的多层基底。

90. 发明申请

US20080132029A1 TRENCH WIDENING WITHOUT MERGING 失效
标题翻译：没有合并的TRENCH扩大
公开(公告)号：US20080132029A1
公开(公告)日：2008-06-05
申请号：US11957615
申请日：2007-12-17
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/76
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. Next, portions of the blocking layer on the {110} side wall surfaces are removed without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法。首先，提供半导体结构。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。接下来，除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围环境。

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