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81. 发明授权

US06218892B1 Differential circuits employing forward body bias 失效
标题翻译：采用正向偏置的差分电路
公开(公告)号：US06218892B1
公开(公告)日：2001-04-17
申请号：US09256842
申请日：1999-02-24
申请人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
发明人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0812 , H03L7/0995
摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.
摘要翻译：在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

82. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

83. 发明授权

US08513741B2 Logic circuits using carbon nanotube transistors 有权
标题翻译：使用碳纳米管晶体管的逻辑电路
公开(公告)号：US08513741B2
公开(公告)日：2013-08-20
申请号：US13216120
申请日：2011-08-23
申请人： Ali Keshavarzi , Juanita Kurtin , Vivek De
发明人： Ali Keshavarzi , Juanita Kurtin , Vivek De
IPC分类号： H01L51/05
CPC分类号： H03K19/20 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0541 , Y10S977/742 , Y10S977/938
摘要： In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
摘要翻译：根据一些实施例，本文公开了包括碳纳米管场效应晶体管的逻辑电路。

84. 发明授权

US08362573B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08362573B2
公开(公告)日：2013-01-29
申请号：US12787966
申请日：2010-05-26
申请人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
发明人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属层与第一源区电耦合。第一金属层和第一扩散区域与第一距离重叠。第二金属层与第一漏极区域和第二漏极区域电耦合。第二金属层和第一扩散区域与第二距离重叠。第一距离大于第二距离。

85. 发明授权

US08004043B2 Logic circuits using carbon nanotube transistors 有权
标题翻译：使用碳纳米管晶体管的逻辑电路
公开(公告)号：US08004043B2
公开(公告)日：2011-08-23
申请号：US11613134
申请日：2006-12-19
申请人： Ali Keshavarzi , Juanita Kurtlin , Vivek De
发明人： Ali Keshavarzi , Juanita Kurtlin , Vivek De
IPC分类号： H01L51/05
CPC分类号： H03K19/20 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0541 , Y10S977/742 , Y10S977/938
摘要： In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
摘要翻译：根据一些实施例，本文公开了包括碳纳米管场效应晶体管的逻辑电路。

86. 发明授权

US07859081B2 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US07859081B2
公开(公告)日：2010-12-28
申请号：US11731543
申请日：2007-03-29
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

87. 发明申请

US20090003028A1 Carbon nanotube fuse element 有权
标题翻译：碳纳米管熔丝元件
公开(公告)号：US20090003028A1
公开(公告)日：2009-01-01
申请号：US11824321
申请日：2007-06-29
申请人： Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
发明人： Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
IPC分类号： G11C17/00 , H01L29/06
CPC分类号： G11C17/16 , B82Y10/00 , G11C13/025 , G11C17/165 , G11C2213/17 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
摘要翻译：在本发明的一个实施例中，用于一次可编程存储器的熔丝元件可以包括耦合到第一晶体管节点和第二晶体管节点的碳纳米管。碳纳米管可以具有在以低电流水平编程存储器单元时可以改变的第一电阻。

88. 发明申请

US20060267093A1 Floating-body dynamic random access memory and method of fabrication in tri-gate technology 有权
公开(公告)号：US20060267093A1
公开(公告)日：2006-11-30
申请号：US11429490
申请日：2006-05-04
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

89. 发明申请

US20060187706A1 2-Transistor floating-body dram 有权
标题翻译： 2晶体管浮体电容
公开(公告)号：US20060187706A1
公开(公告)日：2006-08-24
申请号：US11008666
申请日：2005-02-22
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译：动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

90. 发明申请

US20060139995A1 One time programmable memory 审中-公开
标题翻译：一次可编程存储器
公开(公告)号：US20060139995A1
公开(公告)日：2006-06-29
申请号：US11027476
申请日：2004-12-28
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C17/146 , G11C17/12
摘要： A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
摘要翻译：一次性可编程存储器包括隔离栅极晶体管，其可以通过使隔离栅极晶体管受到降低隔离栅极晶体管特性的电压条件而被编程。可以感测劣化的特性以读取存储器。

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