专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08200471B2 Apparatus and methods for modeling power characteristics of electronic circuitry 有权
标题翻译：用于建模电子电路功率特性的装置和方法
公开(公告)号：US08200471B2
公开(公告)日：2012-06-12
申请号：US12534103
申请日：2009-07-31
申请人： David Lewis , Thomas Yau-Tsun Wong
发明人： David Lewis , Thomas Yau-Tsun Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.
摘要翻译：公开并描述了用于计算诸如可编程逻辑器件（PLD）的集成电路（IC）内的电路的功耗的装置和方法。估计IC中的电路的功耗的方法包括将IC分解为多个重叠块。多个块中的每个块包括IC中的电路的一部分。该方法还包括估计多个块中的每个块的功率消耗，以及基于多个块的功耗来估计IC的功耗。

82. 外观设计

USD634733S1 Subwoofer 有权
标题翻译：超低音扬声器
公开(公告)号：USD634733S1
公开(公告)日：2011-03-22
申请号：US29356041
申请日：2010-02-18
申请人： David Lewis
设计人： David Lewis

83. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

84. 发明申请

US20100284408A1 SYSTEM FOR RECEIVING TRANSPORT STREAMS 有权
标题翻译：运输流程系统
公开(公告)号：US20100284408A1
公开(公告)日：2010-11-11
申请号：US12778413
申请日：2010-05-12
申请人： David Lewis , Howard Gurney
发明人： David Lewis , Howard Gurney
IPC分类号： H04L12/56
CPC分类号： H04N21/4383 , H04N21/42646 , H04N21/42661 , H04N21/42669 , H04N21/42692 , H04N21/434 , H04N21/44004
摘要： A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.
摘要翻译：一种系统，包括用于从外部源接收传输流的第一输入装置，用于从存储器接收输入的第二输入装置，用于将第一和第二输入装置连接到被配置为向解码器提供输出流的接口的装置。第二输入装置被布置成以这样的形式向接口提供输出，使得接口不区分来自第一和第二输入装置的输出。

85. 外观设计

USD614481S1 Framework connector 有权
标题翻译：框架连接器
公开(公告)号：USD614481S1
公开(公告)日：2010-04-27
申请号：US29336322
申请日：2009-04-30
申请人： David Lewis
设计人： David Lewis

86. 发明授权

US07693700B1 Caching technique for electrical simulation of VLSI interconnect 失效
标题翻译： VLSI互连电气仿真缓存技术
公开(公告)号：US07693700B1
公开(公告)日：2010-04-06
申请号：US10462031
申请日：2003-06-13
申请人： Tim Vanderhoek , David Lewis
发明人： Tim Vanderhoek , David Lewis
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/82
摘要： Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.
摘要翻译：包括互连寄生效应的电路，方法和设备，而不会大大增加电路仿真的复杂性和运行时间。基于路径宽度，长度或其他参数，互连路径减少到许多简化拓扑之一。输入驱动波形类似地近似。预先形成网格阵列，其中网格阵列中的每个点对应于与路径拓扑，输入波形和所得到的输出波形相关的一组值。简化的互连路径和输入波形被映射到对应于预定网格阵列中的位置的一组参数中。输出波形通过从位置周围的网格点内插输出波形来确定。

87. 外观设计

USD607109S1 Dental equipment 有权
标题翻译：牙科设备
公开(公告)号：USD607109S1
公开(公告)日：2009-12-29
申请号：US29323080
申请日：2008-08-18
申请人： David Lewis
设计人： David Lewis

88. 发明申请

US20090289696A1 Apparatus and Methods for Adjusting Performance of Integrated Circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US20090289696A1
公开(公告)日：2009-11-26
申请号：US12534101
申请日：2009-07-31
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

89. 发明授权

US07619443B1 Programmable logic device architectures and methods for implementing logic in those architectures 有权
标题翻译：可编程逻辑器件架构和方法，用于在这些架构中实现逻辑
公开(公告)号：US07619443B1
公开(公告)日：2009-11-17
申请号：US11356762
申请日：2006-02-16
申请人： Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
发明人： Tim Vanderhoek , Vaughn Betz , David Cashman , David Lewis , Michael Hutton
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.
摘要翻译：可编程逻辑器件（“PLD”）架构包括被称为逻辑阵列块（LABs“）的集群在一起的逻辑元件（”LE“）。为了保存区域，本地反馈资源（用于将LAB中的LE的输出馈送回到与现有技术相比，减少或消除了LAB中的LE的输入），因为在LAB中一起工作的LE的任何LE输出到LE输入连接的所有（或至少更多）必须是通过LAB的通用输入路由资源路由，重要的是保存这些资源，例如，通过更加重视找到具有共同输入的逻辑功能，在决定在劳顾会

90. 发明授权

US07573317B2 Apparatus and methods for adjusting performance of integrated circuits 有权
标题翻译：用于调整集成电路性能的装置和方法
公开(公告)号：US07573317B2
公开(公告)日：2009-08-11
申请号：US11535065
申请日：2006-09-26
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K3/01
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
摘要翻译：可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。体偏置发生器被配置为调整用户电路内的晶体管的体偏置。体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式