专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07675338B2 Duty cycle correction circuit whose operation is largely independent of operating voltage and process 失效
标题翻译：工作循环校正电路的工作原理很大程度上与工作电压和工艺无关
公开(公告)号：US07675338B2
公开(公告)日：2010-03-09
申请号：US12140335
申请日：2008-06-17
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种占空比校正（DCC）电路，其中已知DCC电路拓扑中的成对的场效应晶体管（FET）被连接到DCC电路的开关的线性电阻器代替，使得当开关断开时，输入信号被路由通过线性电阻。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

82. 发明申请

US20090125857A1 Design Structure for an Absolute Duty Cycle Measurement Circuit 失效
标题翻译：绝对占空比测量电路的设计结构
公开(公告)号：US20090125857A1
公开(公告)日：2009-05-14
申请号：US12129945
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/84
摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
摘要翻译：提供了用于测量信号的绝对占空比的电路的设计结构。选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。然后基于第一和第二最小脉冲宽度值的差来计算占空比。

83. 发明授权

US07519498B2 Thermal sensing method and apparatus using existing ESD devices 有权
标题翻译：使用现有ESD器件的热感测方法和设备
公开(公告)号：US07519498B2
公开(公告)日：2009-04-14
申请号：US11242675
申请日：2005-10-04
申请人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F3/00
CPC分类号： G01K7/01 , G01K2217/00
摘要： The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.
摘要翻译：本发明提供了一种通过使用ESD电路来测量微处理器的温度的方法，装置和计算机程序产品。本发明在ESD电路中使用二极管和I / O焊盘来确定ESD电路位置处的温度。首先，电流测量装置连接到二极管。用户或计算机程序禁用受保护的组件或电路，然后将预定电压施加到I / O焊盘。这通过二极管产生反向饱和电流，由电流测量装置测量。从该电流，用户或计算机程序通过使用二极管反向饱和电流和相应温度的图形表示来确定微处理器在二极管处的温度。

84. 发明授权

US07493229B2 Adjusting voltage for a phase locked loop based on temperature 失效
标题翻译：基于温度调节锁相环的电压
公开(公告)号：US07493229B2
公开(公告)日：2009-02-17
申请号：US11780498
申请日：2007-07-20
申请人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
发明人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
IPC分类号： G01K3/00 , G06F15/00
CPC分类号： H03L1/022 , H03L1/026 , H03L7/0995
摘要： A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要翻译：一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）来控制集成电路器件，相关冷却系统和高频PLL的操作的机构被提供。通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。此外，通过补偿温度来提高PLL电路的工作范围。

85. 发明申请

US20090024349A1 ADJUSTING VOLTAGE FOR A PHASE LOCKED LOOP BASED ON TEMPERATURE 失效
标题翻译：基于温度调节相位锁定环路的电压
公开(公告)号：US20090024349A1
公开(公告)日：2009-01-22
申请号：US11780498
申请日：2007-07-20
申请人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
发明人： David W. Boerstler , Nathaniel R. Chadwick , Eskinder Hailu , Kirk D. Peterson , Jieming Qi
IPC分类号： G06F15/00 , H03L1/02
CPC分类号： H03L1/022 , H03L1/026 , H03L7/0995
摘要： A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要翻译：一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）来控制集成电路器件，相关冷却系统和高频PLL的操作的机构被提供。通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。此外，通过补偿温度来提高PLL电路的工作范围。

86. 发明申请

US20090007047A1 Design Structure for a Phase Locked Loop with Stabilized Dynamic Response 有权
标题翻译：具有稳定动态响应的锁相环的设计结构
公开(公告)号：US20090007047A1
公开(公告)日：2009-01-01
申请号：US12128678
申请日：2008-05-29
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50 , H03L7/085
CPC分类号： H03L7/099 , H03L7/093 , H03L7/183 , H03L2207/04
摘要： A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.
摘要翻译：提供了一种用于获得稳定的动态响应和阻尼因子和环路带宽的独立调整的混合锁相环（PLL）电路的设计结构。说明性实施例的混合PLL电路包括常规RC PLL的电阻/电容（RC）滤波器元件以及从相位频率检测器的输出到压控振荡器（VCO）的前馈路径。混合PLL本质上通过提供RC滤波器来增强常规前馈PLL的性能，RC滤波器的组件可以被加权，以提供对参数变化敏感性较低的动态响应，并且允许环路带宽优化而不牺牲阻尼。

87. 发明申请

US20080186104A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
公开(公告)号：US20080186104A1
公开(公告)日：2008-08-07
申请号：US12098490
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

88. 发明申请

US20080136480A1 Extracting a Maximum Pulse Width of a Pulse Width Limiter 审中-公开
标题翻译：提取脉冲宽度限制器的最大脉冲宽度
公开(公告)号：US20080136480A1
公开(公告)日：2008-06-12
申请号：US12034039
申请日：2008-02-20
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017 , H03K7/08
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus for extracting a maximum pulse width of a pulse width limiter is provided. The apparatus performs such extraction using a circuit that is configured to eliminate a majority of delay cells. The elimination of delay cells is made possible by replacing an OR gate in the circuit configuration with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供一种用于提取脉冲宽度限制器的最大脉冲宽度的装置。该装置使用被配置为消除大多数延迟单元的电路来执行这种提取。通过用边沿触发的可重新设置的锁存器替换电路配置中的或门，可以实现消除延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

89. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

90. 发明授权

US07260491B2 Duty cycle measurement apparatus and method 失效
公开(公告)号：US07260491B2
公开(公告)日：2007-08-21
申请号：US11260570
申请日：2005-10-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式