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81. 发明申请

US20130215667A1 Circuits And Techniques To Compensate Data Signals For Variations Of Parameters Affecting Memory Cells In Cross-Point Arrays 有权
标题翻译：电路和技术补偿数据信号变化参数影响存储器单元在交叉点数组
公开(公告)号：US20130215667A1
公开(公告)日：2013-08-22
申请号：US13728676
申请日：2012-12-27
申请人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C13/00
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为补偿影响存储器元件的操作的参数变化，诸如基于第三维存储器的存储器元件技术。在至少一些实施例中，集成电路包括交叉点阵列，其包括布置在字线和位线之间的存储器元件，其中参数可影响存储器元件的操作特性。集成电路还包括数据信号调整器，其被配置为基于该参数来修改操作特性以补偿与操作特性的目标值的偏差。在一些实施例中，诸如电阻性存储器元件的存储器元件被配置为生成具有与参数变化无关的基本上在目标值的幅度的数据信号。

82. 发明申请

US20130016681A1 AUTOMATED PARAMETER ADJUSTMENT TO COMPENSATE SELF ADJUSTING TRANSMIT POWER AND SENSITIVITY LEVEL AT THE NODE B 有权
公开(公告)号：US20130016681A1
公开(公告)日：2013-01-17
申请号：US13621674
申请日：2012-09-17
申请人： Aziz GHOLMIEH , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
发明人： Aziz GHOLMIEH , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
IPC分类号： H04W52/04 , H04W74/08
CPC分类号： H04W52/10 , H04W52/244 , H04W52/246 , H04W52/367
摘要： A small base node such as a Home Base Node (HNB), or femto cell, may reduce its transmit power in order to prevent co-channel or adjacent channel interference, or to limit its coverage area. Once the power is set, the HNB signal to a served Home User Equipment (HUE) its transmit Common Pilot Channel (CPICH) transmit power for accurate path loss estimation. When this power is outside of the permissible range, the HNB adjusts other parameters (such as Random Access Channel (RACH) constant value) to compensate for the error in signaled CPICH power, and thus compensate in that process the error in determining path loss. Similarly, if the uplink sensitivity is adjusted, to prevent interference, parameters would also be adjusted and signaled to the HUE to reflect the link imbalance.

83. 发明申请

US20110188291A1 Preservation circuit and methods to maintain values representing data in one or more layers of memory 失效
标题翻译：保存电路和保持在一层或多层存储器中表示数据的值的方法
公开(公告)号：US20110188291A1
公开(公告)日：2011-08-04
申请号：US12932637
申请日：2011-03-01
申请人： Christophe Chevallier , Robert Norman
发明人： Christophe Chevallier , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
摘要翻译：公开了用于恢复存储器中的数据的电路和方法。存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

84. 发明申请

US20100203892A1 SYSTEM AND METHOD FOR INTERFERENCE BEACON TRANSMISSION 失效
标题翻译：用于干扰信号传输的系统和方法
公开(公告)号：US20100203892A1
公开(公告)日：2010-08-12
申请号：US12702714
申请日：2010-02-09
申请人： Sumeeth Nagaraja , Mehmet Yavuz , Farhad Meshkati , Christophe Chevallier
发明人： Sumeeth Nagaraja , Mehmet Yavuz , Farhad Meshkati , Christophe Chevallier
IPC分类号： H04W36/00
CPC分类号： H04W36/30 , H04W84/045
摘要： Various systems and methods for interference beacon transmission are disclosed. In one embodiment, an apparatus for initiating cell reselection in a wireless communication device, such as a HNB, comprises a processor configured to determine a first frequency at which one or more wireless communication devices communicate with a first cell and a transceiver configured to transmit an interference beacon at the first frequency configured to at least partially interfere with communications at the first frequency and initiate a cell reselection process by at least one of the wireless communication devices.
摘要翻译：公开了用于干扰信标传输的各种系统和方法。在一个实施例中，用于在无线通信设备（例如HNB）中发起小区重选的设备包括处理器，其被配置为确定一个或多个无线通信设备与第一小区通信的第一频率和被配置为发送第一频率的干扰信标被配置为至少部分地干扰在第一频率的通信，并且由至少一个无线通信设备发起小区重选过程。

85. 发明申请

US20050281120A1 Memory system, method and predeconding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure 有权
标题翻译：可在不同模式下操作的存储器系统，方法和预分解电路，用于选择性地访问存储器单元的多个块以用于同时写入或擦除
公开(公告)号：US20050281120A1
公开(公告)日：2005-12-22
申请号：US11212328
申请日：2005-08-26
申请人： Vinod Lakhani , Christophe Chevallier , Mathew Adsitt
发明人： Vinod Lakhani , Christophe Chevallier , Mathew Adsitt
IPC分类号： G11C7/10 , G11C8/00 , G11C8/12 , G11C16/08
CPC分类号： G11C7/1045 , G11C8/12 , G11C16/08
摘要： A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.
摘要翻译：公开了一种包括非易失性闪速存储器和用于同时选择多个存储块的方法的存储器系统。存储器系统被组织成多个主块，每个主块具有多个较小的块，模拟磁盘驱动器。控制线激活多种模式。在第一模式中，高阶地址线仅选择一个块，而在第二模式中，选择用户指定的多个块。通过加载具有选择位的寄存器或直接使用某些地址线作为选择位来选择块。每个位指定一个块，每个位独立于其他位。存储器系统还包括预解码器和控制器，其控制预解码器和寄存器以便选择至少两个存储单元块。在第三模式中，选择所有块，并且在第四模式中，所有块都被取消选择。选择多个块可以同时擦除，写入和读取存储在存储器中的多个字节。

86. 发明申请

US20050270836A1 Erase verify for non-volatile memory 有权
公开(公告)号：US20050270836A1
公开(公告)日：2005-12-08
申请号：US11198197
申请日：2005-08-05
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

87. 发明申请

US20050270835A1 Erase verify for non-volatile memory 有权
公开(公告)号：US20050270835A1
公开(公告)日：2005-12-08
申请号：US11198196
申请日：2005-08-05
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

88. 发明申请

US20050207224A1 Flash memory with fast boot block access 失效
标题翻译：具有快速启动块访问的闪存
公开(公告)号：US20050207224A1
公开(公告)日：2005-09-22
申请号：US11130357
申请日：2005-05-16
申请人： Christophe Chevallier , Allahyar Vahidimowlavi
发明人： Christophe Chevallier , Allahyar Vahidimowlavi
IPC分类号： G11C16/04 , G11C16/20 , G11C16/26 , G11C16/30
CPC分类号： G11C16/20 , G11C16/26 , G11C16/30
摘要： A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.
摘要翻译：闪存设备和系统包括用于向闪存的引导块提供字线电压的引导块电压泵。提供至少一个额外的电压泵以向剩余的存储器块提供字线电压。可以根据规范来操作存储器件，其中存储在引导块中的数据可以被读取为有效数据，在存储在其它存储器块中的数据可以在存储器激活时被有效读取。

89. 发明授权

US06948041B2 Permanent memory block protection in a flash memory device 失效
标题翻译：闪存设备中的永久存储块保护
公开(公告)号：US06948041B2
公开(公告)日：2005-09-20
申请号：US10279470
申请日：2002-10-24
申请人： Christophe Chevallier , See Kit Leong
发明人： Christophe Chevallier , See Kit Leong
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A secure command is entered into a Flash memory device. A control data word is written to the memory device to specify which blocks of memory are to be permanently secured against write and erase operations. The bits of the control data word specify different blocks of memory to be permanently secured.
摘要翻译：闪存设备中输入安全命令。将控制数据字写入存储器设备，以指定要对写入和擦除操作永久地保护哪些存储器块。控制数据字的位指定要永久保护的不同的存储块。

90. 发明授权

US06944839B2 Checking layout accuracy in integrated circuit designs 失效
标题翻译：检查集成电路设计中的布局精度
公开(公告)号：US06944839B2
公开(公告)日：2005-09-13
申请号：US10782247
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method for checking layout accuracy in an integrated circuit design includes creating a schematic, adding a line width marker to selected lines having a width greater than an absolute minimum width, and assigning a line width to each line width marker. A layout is created and is checked versus the schematic. A design is extracted from the layout. The design has a design line width corresponding to each line having a line width marker. The design line width is checked versus the marker line width for each line having a line width marker.
摘要翻译：一种用于检查集成电路设计中的布局精度的方法包括创建示意图，将线宽标记添加到具有大于绝对最小宽度的宽度的所选择的线，以及为每个线宽标记分配线宽。创建布局并检查相对于原理图。从布局中提取设计。该设计具有对应于具有线宽标记的每一行的设计线宽度。对于具有线宽标记的每一行，检查设计线宽度与标记线宽度。

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