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81. 发明授权

US06259142B1 Multiple split gate semiconductor device and fabrication method 失效
标题翻译：多分裂栅极半导体器件及其制造方法
公开(公告)号：US06259142B1
公开(公告)日：2001-07-10
申请号：US09056837
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2976
CPC分类号： H01L29/66484 , H01L29/7831
摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.
摘要翻译：具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

82. 发明授权

US06201278B1 Trench transistor with insulative spacers 失效
标题翻译：带绝缘垫片的沟槽晶体管
公开(公告)号：US06201278B1
公开(公告)日：2001-03-13
申请号：US09028896
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31062
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

83. 发明授权

US6100146A Method of forming trench transistor with insulative spacers 失效
标题翻译：用绝缘间隔物形成沟槽晶体管的方法
公开(公告)号：US6100146A
公开(公告)日：2000-08-08
申请号：US739595
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

84. 发明授权

US06080629A Ion implantation into a gate electrode layer using an implant profile displacement layer 失效
标题翻译：使用植入物轮廓位移层将离子注入到栅极电极层中
公开(公告)号：US06080629A
公开(公告)日：2000-06-27
申请号：US837579
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28035
摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要翻译：将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

85. 发明授权

US6048785A Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching 失效
标题翻译：半导体制造方法，其使用片段拼接来组合由标线片图像定义的多个场
公开(公告)号：US6048785A
公开(公告)日：2000-04-11
申请号：US876628
申请日：1997-06-16
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , Y10S438/946 , Y10S438/949
摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要翻译：在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

86. 发明授权

US5937299A Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls 失效
标题翻译：用于形成具有硅化物源极/漏极接触的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US5937299A
公开(公告)日：1999-08-10
申请号：US837522
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/0847 , H01L29/41775 , H01L29/42376 , H01L29/66628 , H01L29/665
摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

87. 发明授权

US5918126A Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size 失效
标题翻译：使用偏置差分制造具有不同器件密度的器件的集成电路的制造方法，以形成具有均匀尺寸的器件
公开(公告)号：US5918126A
公开(公告)日：1999-06-29
申请号：US805796
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/8234
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/823456
摘要： It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates. More specifically, in one embodiment the polysilicon masking reticle is increased in size in regions of high density polysilicon gates in comparison to regions of isolated polysilicon gates. In another embodiment, the reticle in regions of isolated polysilicon gates is sized normally but increased in size in regions of high density polysilicon gates. Following photomasking and etching, substantially identical polysilicon lengths are achieved in the isolated and dense gate regions.
摘要翻译：已经发现，与低密度（隔离）多晶硅栅极区域相比，在常规光刻中发生的不同图案密度在多晶硅栅极的高密度（密集）区域中产生不同的最终蚀刻多晶硅栅极宽度。用于密集区域的最终蚀刻多晶硅栅极宽度相对于隔离区域的最终蚀刻多晶硅栅极宽度可预测的距离较小。例如，典型的密集区域具有最终蚀刻多晶硅栅极宽度，相对于沟道长度为0.35μm的隔离区域的最终蚀刻多晶硅栅极宽度大约为0.05μm。对于多晶硅掩模掩模版采用偏置技术，其中与致密多晶硅栅极的区域相比，掩模版在隔离多晶硅栅极的区域中被不同地偏置。更具体地，在一个实施例中，与隔离多晶硅栅极的区域相比，多晶硅掩模掩模版的尺寸在高密度多晶硅栅极的区域中增加。在另一个实施例中，隔离多晶硅栅极的区域中的掩模版尺寸正常，但在高密度多晶硅栅极的区域中的尺寸增大。在光掩模和蚀刻之后，在隔离和密集的栅极区域中实现了基本相同的多晶硅长度。

88. 发明授权

US5851891A IGFET method of forming with silicide contact on ultra-thin gate 失效
标题翻译： IGFET在超薄栅极上与硅化物接触形成的方法
公开(公告)号：US5851891A
公开(公告)日：1998-12-22
申请号：US837521
申请日：1997-04-21
申请人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/4933 , H01L29/665
摘要： An IGFET with a silicide contact on an ultra-thin gate is disclosed. A method of forming the IGFET includes forming a gate over a semiconductor substrate, forming a source and a drain in the substrate, depositing a contact material over the gate, and reacting the contact material with the gate to form a silicide contact on the gate and consume at least one-half of the gate. By consuming such a large amount of the gate, a relatively thin gate can be converted into an ultra-thin gate with a thickness on the order of 100 to 200 angstroms. Preferably, the bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a peak concentration of a dopant in the gate towards the substrate so that a heavy concentration of the dopant is pushed to the bottom surface of the gate without being pushed into the substrate. As exemplary materials, the contact material is a refractory metal such as titanium, the gate is polysilicon, and the dopant is arsenic.
摘要翻译：公开了一种在超薄栅极上具有硅化物接触的IGFET。形成IGFET的方法包括在半导体衬底上形成栅极，在衬底中形成源极和漏极，在栅极上沉积接触材料，并使接触材料与栅极反应以在栅极上形成硅化物接触，以及消耗至少一半的门。通过消耗大量的栅极，可以将相对薄的栅极转换成厚度在100至200埃左右的超薄栅极。优选地，栅极的底表面在使接触材料与栅极反应之前基本上是未掺杂的，并且使接触材料与栅极反应将栅极中的掺杂剂的峰值浓度推向衬底，使得掺杂剂的重浓度为被推入门的底表面而不被推入基板。作为示例性材料，接触材料是诸如钛的难熔金属，栅极是多晶硅，掺杂剂是砷。

89. 发明授权

US5840451A Individually controllable radiation sources for providing an image pattern in a photolithographic system 失效
标题翻译：用于在光刻系统中提供图像图案的可单独控制的辐射源
公开(公告)号：US5840451A
公开(公告)日：1998-11-24
申请号：US760029
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F7/20 , G03F9/00
CPC分类号： G03F7/70391 , G03F7/20 , Y10S430/146 , Y10S430/168
摘要： A photolithographic system includes individually controllable radiation sources for forming an image pattern on an image plane without using a reticle or mask during fabrication of an integrated circuit device. The radiation sources are selectively activated as they scan the image plane. The image pattern can consist of parallel lines having identical widths and varying lengths, or alternatively, pixels having identical shapes and sizes. The radiation sources can be arranged as a linear array, or a staggered array, to achieve the desired linear density. Suitable radiation sources include light pipes, light emitting diodes, and laser diodes. Preferably, each of the activated radiation sources provides an exposure field of less than 0.1 microns on the image plane, and at least two of the radiation sources must be activated to provide the minimum line width of the image pattern.
摘要翻译：光刻系统包括单独可控的辐射源，用于在集成电路器件的制造期间在图像平面上形成图像图案而不使用掩模版或掩模。当扫描图像平面时，辐射源被选择性地激活。图像图案可以由具有相同宽度和变化长度的平行线组成，或者替代地，具有相同形状和尺寸的像素。辐射源可以被布置为线性阵列或交错阵列，以实现期望的线密度。合适的辐射源包括光管，发光二极管和激光二极管。优选地，每个激活的辐射源在图像平面上提供小于0.1微米的曝光场，并且必须激活至少两个辐射源以提供图像图案的最小线宽。

90. 发明授权

US5801075A Method of forming trench transistor with metal spacers 失效
标题翻译：用金属间隔物形成沟槽晶体管的方法
公开(公告)号：US5801075A
公开(公告)日：1998-09-01
申请号：US739593
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

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