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81. 发明授权

US07383493B2 LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance 有权
标题翻译：使用非格雷码的LDPC（低密度奇偶校验）编码调制混合解码，以提高性能
公开(公告)号：US07383493B2
公开(公告)日：2008-06-03
申请号：US10802011
申请日：2004-03-16
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H04L1/005 , G11B20/1833 , H03M13/1102 , H03M13/1105 , H03M13/1117 , H03M13/112 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6583 , H04L1/0041 , H04L1/0058 , H04L1/006 , H04L1/0071 , H04L1/1671 , H04L27/18 , H04L27/2602
摘要： LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.
摘要翻译：使用非格雷码的LDPC（低密度奇偶校验）编码调制混合解码，以提高性能。对于预定数量的解码迭代，或者直到达到足够的精度，连续替代地对位边消息执行检查节点更新和符号节点更新。比特边消息的符号节点更新使用与正被解码的符号相对应的符号度量和最近由校验节点更新更新的位边消息。位边消息的校验节点更新使用最近由符号节点更新更新的位边消息。符号节点更新计算可能的软符号估计。 LDPC编码调制混合解码可以解码具有使用非格雷码映射的符号映射的LDPC-BICM（低密度奇偶校验位交错编码调制）信号。通过使用非格雷码映射，仅通过格雷码映射系统实现性能提升。

82. 发明授权

US07383485B2 Fast min*- or max*-circuit in LDPC (low density parity check) decoder 失效
标题翻译： LDPC（低密度奇偶校验）解码器中的快速最小*或最大*电路
公开(公告)号：US07383485B2
公开(公告)日：2008-06-03
申请号：US11172329
申请日：2005-06-30
申请人： Hau Thien Tran , Kelly Brian Cameron , Ba-Zhong Shen
发明人： Hau Thien Tran , Kelly Brian Cameron , Ba-Zhong Shen
IPC分类号： H03M13/45
CPC分类号： H03M13/112 , H03M13/1105 , H03M13/1117 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2906 , H03M13/6583 , H04L1/0003 , H04L1/0057
摘要： Fast min*− (min-star-minus) or max*− (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*− and/or min*− processing allows for very fast operation when compared to prior art approaches.
摘要翻译： LDPC（低密度奇偶校验）解码器中的快速min * - （min-star-minus）或max * - （max-star-minus）电路。提出了一种新颖有效的方法，通过该方法可以在各种类型的解码器中执行校验节点处理所需的某些计算。这里呈现的功能和体系结构可应用于LDPC解码器，并且还可以用于可操作以解码其他类型的编码信号的其他类型的解码器。与现有技术方法相比，最大*和/或最小*处理的总体结果的某些部分的并行和有时同时的计算和确定允许非常快速的操作。

83. 发明申请

US20080115033A1 Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves 有权
标题翻译：具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成
公开(公告)号：US20080115033A1
公开(公告)日：2008-05-15
申请号：US11810989
申请日：2007-06-07
申请人： Tak K. Lee , Ba-Zhong Shen
发明人： Tak K. Lee , Ba-Zhong Shen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2771 , H03M13/276 , H03M13/2957 , H03M13/6561 , H04L1/005 , H04L1/0066
摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function , that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function of also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.
摘要翻译：具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。提出了一种新颖的方法，其中使用索引函数采用预期地址生成，这是基于地址映射，其对应于解码处理（pi ^{-1）的交织逆序。根据并行turbo解码处理，代替通过依次从存储体单元访问数据元素来执行自然次序相位解码处理，基于索引函数，这是基于映射和交织）。换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。索引函数还允许通过从存储体位置顺序地访问数据元素来执行交织（pi）阶相位解码处理。}

84. 发明授权

US07370265B2 Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps 有权
标题翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案
公开(公告)号：US07370265B2
公开(公告)日：2008-05-06
申请号：US11701155
申请日：2007-02-01
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M5/20 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1148 , H03M13/1177 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6561 , H04L1/0041 , H04L1/0058 , H04L1/006 , H04L1/0071 , H04L27/18 , H04L27/183 , H04L27/186 , H04L27/2053
摘要： Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords (e.g., an MLC block) are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks that corporately form an MLC block. Encoded bits from levels of the MLC block are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.
摘要翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案。多个地图的使用适用于各种类型的编码信号，包括多级LDPC编码调制信号和其他MLC信号，以便在试图达到香农限制的持续努力中提供显着的性能增益。在LDPC编码信号的情况下，从各自对应的LDPC编码器生成各种级别的LDPC码字（例如，MLC块）。这些各种级别的LDPC码字被排列成合并形成MLC块的多个子块。 MLC块的编码比特被排列成根据至少两个调制映射的符号。每个调制包括星座形状和相应的映射。与仅使用单个映射的编码器相比，使用多个映射提供了改进的性能。

85. 发明授权

US07321633B1 Determination of variable code rates for a rate control sequence 有权
标题翻译：确定速率控制序列的可变代码率
公开(公告)号：US07321633B1
公开(公告)日：2008-01-22
申请号：US10338432
申请日：2003-01-08
申请人： Kelly Brian Cameron , Ba-Zhong Shen , Hau Thien Tran
发明人： Kelly Brian Cameron , Ba-Zhong Shen , Hau Thien Tran
IPC分类号： H04L23/02
CPC分类号： H04L27/0008 , H04L1/0009 , H04L1/0041 , H04L1/005 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L2001/0098
摘要： Determination of variable code rates for a rate control sequence. A rate control sequence governs symbols that are to be encoded and/or decoded. A different rate control value may be used to control code rates of individual symbols in a signal. The determination of the variable code rates may be performed based on a number of parameters including a communication system's operating conditions and/or the signal to noise ratio (SNR) of a communication channel. The variable code rates may also adaptively change, in real time (if desired), in response to the communication system's operating conditions including a communication channel's SNR. The variable code rate functionality may also be adaptively tailored to match the SNR of a communication receiver's communication channel within a multi-receiver communication system; those receivers in a beam spot (higher SNR) may operate using a higher code rate than those receivers further away from the spot (lower SNR).
摘要翻译：确定速率控制序列的可变代码率。速率控制序列控制要被编码和/或解码的符号。可以使用不同的速率控制值来控制信号中的各个符号的码率。可以基于包括通信系统的操作条件和/或通信信道的信噪比（SNR）的参数的数量来执行可变码率的确定。响应于包括通信信道的SNR的通信系统的操作条件，可变码率也可以实时（如果需要）自适应地改变。也可以自适应地定制可变码率功能以匹配多接收机通信系统内的通信接收机的通信信道的SNR; 波束点（较高SNR）中的那些接收机可以使用比远离该点（较低SNR）的那些接收机更高的码率来操作。

86. 发明授权

US07296216B2 Stopping and/or reducing oscillations in low density parity check (LDPC) decoding 有权
标题翻译：停止和/或减少低密度奇偶校验（LDPC）解码中的振荡
公开(公告)号：US07296216B2
公开(公告)日：2007-11-13
申请号：US10370136
申请日：2003-02-19
申请人： Ba-Zhong Shen , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Kelly Brian Cameron
IPC分类号： G06F11/00
CPC分类号： H03M13/658 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/3738 , H03M13/3746
摘要： Stopping or reducing oscillations in Low Density Parity Check (LDPC) codes. A novel solution is presented that completely eliminates and/or substantially reduces the oscillations that are oftentimes encountered with the various iterative decoding approaches that are employed to decode LDPC coded signals. This novel approach may be implemented in any one of the following three ways. One way involves combining the Sum-Product (SP) soft decision decoding approach with the Bit-Flip (BF) hard decision decoding approach in an intelligent manner that may adaptively select the number of iterations performed during the SP soft decoding process. The other two ways involve modification of the manner in which the SP soft decoding approach and the BF hard decision decoding approach are implemented. One modification involves changing the initialization of the SP soft decoding process, and another modification involves the updating procedure employed during the SP soft decoding approach process.
摘要翻译：停止或减少低密度奇偶校验（LDPC）码中的振荡。提出了一种新颖的解决方案，其完全消除和/或基本上减少了用于解码LDPC编码信号的各种迭代解码方法经常遇到的振荡。这种新颖的方法可以以以下三种方式中的任何一种来实现。一种方式是将Sum-Product（SP）软判决解码方法与智能方式的Bit-Flip（BF）硬判决解码方法相结合，可以自适应地选择在SP软解码过程中执行的迭代次数。另外两种方式涉及SP软解码方法和BF硬判决解码方式的实现方式的修改。一个修改涉及改变SP软解码过程的初始化，另一个修改涉及在SP软解码过程中采用的更新过程。

87. 发明授权

US07197690B2 Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps 有权
标题翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案
公开(公告)号：US07197690B2
公开(公告)日：2007-03-27
申请号：US11017087
申请日：2004-12-20
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： H03M13/03
CPC分类号： H04L1/005 , H03M5/20 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1148 , H03M13/1177 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6561 , H04L1/0041 , H04L1/0058 , H04L1/006 , H04L1/0071 , H04L27/18 , H04L27/183 , H04L27/186 , H04L27/2053
摘要： Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.
摘要翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案。多个地图的使用适用于各种类型的编码信号，包括多级LDPC编码调制信号和其他MLC信号，以便在试图达到香农限制的持续努力中提供显着的性能增益。在LDPC编码信号的情况下，从各自对应的LDPC编码器生成各种级别的LDPC码字。这些各种级别的LDPC码字被排列成多个子块。每个子块内的多级LDPC码字的编码比特被排列成根据至少两个调制映射的符号。每个调制包括星座形状和相应的映射。这种使用多个映射

88. 发明授权

US07107511B2 Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses 有权
标题翻译：使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转
公开(公告)号：US07107511B2
公开(公告)日：2006-09-12
申请号：US10369168
申请日：2003-02-19
申请人： Ba-Zhong Shen , Kelly Brian Cameron , Hau Thien Tran
发明人： Ba-Zhong Shen , Kelly Brian Cameron , Hau Thien Tran
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H04L1/0057
摘要： Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.
摘要翻译：使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转。首次演示了用于解码LDPC编码信号的min *处理。另外，当执行执行使用LDPC码编码的信号的解码所需的计算时，也可以采用max *，min **或max **（及其各自的反转）。当解码涉及从多个可能值中确定最小和/或最大值或最小和/或最大对数校正值时，可以采用这些新参数来为LDPC码提供大大改进的解码处理。采用本文所述的最小*，最大*，最小**或最大**（及其相应的反转）解码处理，在LDPC编码信号的解码中采用的处理步骤的总数显着减少。

89. 发明授权

US07065695B2 Metric calculation design for variable code rate decoding of broadband trellis, TCM, or TTCM 失效
标题翻译：宽带网格，TCM或TTCM的可变码率解码的度量计算设计
公开(公告)号：US07065695B2
公开(公告)日：2006-06-20
申请号：US10264647
申请日：2002-10-04
申请人： Kelly Brian Cameron , Ba-Zhong Shen , Hau Thien Tran , Linda K. Lau
发明人： Kelly Brian Cameron , Ba-Zhong Shen , Hau Thien Tran , Linda K. Lau
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H03M13/256 , H03M13/258 , H03M13/27 , H03M13/2767 , H03M13/2771 , H03M13/2785 , H03M13/2957 , H03M13/4123 , H03M13/4161 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.
摘要翻译：宽带网格，TCM（网格编码调制）或TTCM（turbo网格编码调制）的可变码率解码的度量计算设计。单一设计可以通过在设计中复用适当的路径来适应大量的代码率。通过控制在接收信号中对接收到的符号的任何噪声进行缩放的位置，可以以在性能，处理要求（例如乘法器和门）等方面非常有效的方式来实现这种适应性设计，以及房地产消费。在支持多个码率的情况下，使用沿I和Q轴的固有冗余和对称性适当地选择所使用的各种星座的系数，可以大大节省借助于其中包含的固有冗余的门; 此外，当利用这种对称性时，不需要执行减法（但只有求和）。

90. 发明授权

US06691278B1 Detecting errors in coded bit strings 有权
标题翻译：检测编码位串中的错误
公开(公告)号：US06691278B1
公开(公告)日：2004-02-10
申请号：US09418210
申请日：1999-10-13
申请人： Ara Patapoutian , Ba-Zhong Shen , Peter McEwen , Michael Leis
发明人： Ara Patapoutian , Ba-Zhong Shen , Peter McEwen , Michael Leis
IPC分类号： G06F1100
CPC分类号： H03M13/09 , G11B20/1833 , G11B2220/2562 , H03M13/11 , H03M13/15 , H03M13/3944 , H03M13/41
摘要： A parity check matrix is generated for detecting predefined errors in a coded string of bits. A column of the matrix is generated by selecting values for elements in the column and processing a predefined error with the selected values in order to produce a syndrome. The selected values are assigned to the column of the parity check matrix if an element of the syndrome has a value indicative of the predefined error.
摘要翻译：生成奇偶校验矩阵以检测编码比特串中的预定义错误。通过选择列中的元素的值并使用所选值处理预定义的错误来产生矩阵的列，以产生综合征。如果校正子的元素具有指示预定义错误的值，则将所选择的值分配给奇偶校验矩阵的列。

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