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81. 发明授权

US08970411B2 Pipelined continuous-time sigma delta modulator 有权
标题翻译：流水线连续时间Σ-Δ调制器
公开(公告)号：US08970411B2
公开(公告)日：2015-03-03
申请号：US13601795
申请日：2012-08-31
申请人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
发明人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/458
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译：传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。

82. 发明申请

US20130265732A1 INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE 有权
标题翻译：使用介质波导的交互通信
公开(公告)号：US20130265732A1
公开(公告)日：2013-10-10
申请号：US13439557
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： H05K1/0239 , G02B6/12004 , G02B6/1228 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/16 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K1/115 , H05K1/18 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

83. 发明申请

US20120326906A1 PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR 有权
标题翻译：管道连续式SIGMA DELTA调制器
公开(公告)号：US20120326906A1
公开(公告)日：2012-12-27
申请号：US13601795
申请日：2012-08-31
申请人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
发明人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
IPC分类号： H03M3/02
CPC分类号： H03M3/344 , H03M3/458
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译：传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。

84. 发明申请

US20120286981A1 COMPRESSIVE SENSING ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：压缩感测模拟数字转换器
公开(公告)号：US20120286981A1
公开(公告)日：2012-11-15
申请号：US13106585
申请日：2011-05-12
申请人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
发明人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
IPC分类号： H03M1/66
CPC分类号： H03M1/1265
摘要： Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.
摘要翻译：压缩感测是一个新兴领域，它试图防止与数据压缩相关的损失，并提高整体效率，压缩感测在能量浪费之前，在捕获之前或捕获过程中会执行压缩。这里，提供了几个模数转换器（ADC）架构来执行压缩感测。这些新架构中的每一个基本上随机选择每个样本的分辨率，并根据这些选择的分辨率调整采样率。

85. 发明授权

US08248282B2 Track and hold architecture with tunable bandwidth 有权
标题翻译：跟踪和保持具有可调带宽的架构
公开(公告)号：US08248282B2
公开(公告)日：2012-08-21
申请号：US12857674
申请日：2010-08-17
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/00
CPC分类号： H03M1/08 , H03M1/1215
摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
摘要翻译：到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配带宽。

86. 发明申请

US20120106211A1 POWER FACTOR AND LINE DISTORTION METHOD AND APPARATUS 审中-公开
标题翻译：功率因数和线性失真方法和装置
公开(公告)号：US20120106211A1
公开(公告)日：2012-05-03
申请号：US12938958
申请日：2010-11-03
申请人： Marco Corsi , David Freeman , Fernando Mujica
发明人： Marco Corsi , David Freeman , Fernando Mujica
IPC分类号： H02M1/12
CPC分类号： H02M1/4225 , H02M3/157 , Y02B70/126 , Y10T307/406
摘要： Today, power distribution systems can be used to supply power to many loads, and since many loads, such as servers, are reactive (i.e., have capacitors and/or inductors), line distortion and power factor can be an issue. Conventional techniques to correct for line distortion and power factor use a specialized circuit that is generally in series with the load, but these specialized circuits can be prohibitively expensive when used in large numbers. Here, however, a corrective power supply has been provided, which can correct for other parallel power supplies that can reduce cost.
摘要翻译：今天，配电系统可以用于向许多负载供电，并且由于诸如服务器的许多负载是无功的（即，具有电容器和/或电感器），所以线路失真和功率因数可能是一个问题。用于校正线路失真和功率因数的常规技术使用通常与负载串联的专用电路，但是当大量使用时，这些专用电路可能是非常昂贵的。然而，这里提供了一种校正电源，可以校正可以降低成本的其他并联电源。

87. 发明申请

US20120098572A1 LATCHED COMPARATOR HAVING ISOLATION INDUCTORS 有权
标题翻译：具有隔离电感器的锁存比较器
公开(公告)号：US20120098572A1
公开(公告)日：2012-04-26
申请号：US12911456
申请日：2010-10-25
申请人： Vaibhav Tripathi , Marco Corsi , Venkatesh Srinivasan
发明人： Vaibhav Tripathi , Marco Corsi , Venkatesh Srinivasan
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K3/356182
摘要： Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).
摘要翻译：传统上，锁存的比较器遭受与闩锁暴露到负载电容相关的性能问题。即使通过电阻将锁存器与负载电容隔离的尝试也导致性能问题（即电压摆幅降低）。然而，这里提供了一种使用电感器通常提供与负载电容的隔离的锁存比较器，这通常改善了性能。此外，锁存器已被修改以在轨道周期期间容纳电感器（即，提供接地路径）。

88. 发明授权

US07990188B2 Clock buffer 有权
标题翻译：时钟缓冲
公开(公告)号：US07990188B2
公开(公告)日：2011-08-02
申请号：US13017436
申请日：2011-01-31
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.
摘要翻译：提供了一种装置。该装置包括具有第一BJT和第二BJT的第一双极结型晶体管（BJT）差分对，具有第三BJT和第四BJT的第二BJT差分对，具有第五BJT和第六BJT的第一钳位，以及第二夹具具有第七BJT和第八BJT。第三BJT的集电极和基极分别耦合到第一BJT的集电极和基极，并且第四BJT的集电极和基极分别耦合到第二BJT的集电极和基极。第一，第二，第三和第四BJT的基极接收输入时钟信号。第五和第六BJT的发射器耦合到第一和第三BJT的集电极，而第七和第八BJT的发射极耦合到第二和第四BJT的集电极。第五和第七BJT的基极适于接收低钳位电压，并且第六和第八BJT的基极适于接收高钳位电压。另外，第一和第二夹具耦合到第一，第二，第三和第四BJT的收集器。

89. 发明授权

US07906995B2 Clock buffer 有权
公开(公告)号：US07906995B2
公开(公告)日：2011-03-15
申请号：US12393188
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
发明人： Robert F. Payne , Marco Corsi , Tien-Ling Hsieh
IPC分类号： H03B1/00
CPC分类号： H03M1/002 , H03M1/1245
摘要： An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs.

90. 发明授权

US07825846B2 Error correction method and apparatus 有权
标题翻译：纠错方法及装置
公开(公告)号：US07825846B2
公开(公告)日：2010-11-02
申请号：US12393207
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/38
CPC分类号： G05F3/265
摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.
摘要翻译：提供开关电流源。开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

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