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81. 发明授权

US06190961B1 Fabricating a square spacer 失效
标题翻译：制造方形垫片
公开(公告)号：US06190961B1
公开(公告)日：2001-02-20
申请号：US09401050
申请日：1999-09-22
申请人： Chung Hon Lam , Jed Hickory Rankin , Christa Regina Willets , Arthur Paul Johnson
发明人： Chung Hon Lam , Jed Hickory Rankin , Christa Regina Willets , Arthur Paul Johnson
IPC分类号： H01L218242
CPC分类号： H01L29/6659 , H01L21/31116 , H01L21/32137 , H01L29/6656
摘要： A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching, and performing a second etching. The spacer film is formed on perpendicular first and second sides of the mandrel. A first region and a second region of the spacer film are on the first side and the second side of the mandrel, respectively. The spacer film may include a conductive material such as polysilicon or tungsten. The spacer film may alternatively include an insulative material such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide film is formed such that a first region and a second region of the oxide film are on the first region and the second region of the spacer film, respectively. The oxide film may include silicon dioxide. The first etching etches away the first region of the oxide film and a portion of the first region of the spacer film. The second etching forms the square spacer by etching away the remaining first region of the spacer film and also a portion of the second region of the oxide film, after which a top surface of the second region of the spacer film and a top surface of the second region of the oxide film are at about the same height above the substrate. The first and second etching may be accomplished by reactive ion etching or chemical downstream etching.
摘要翻译：方形间隔件和制造方法。该方法包括在定位在基板上的心轴上形成间隔膜，在间隔膜上形成氧化膜，进行第一蚀刻，并进行第二蚀刻。间隔膜形成在心轴的垂直的第一和第二侧上。间隔膜的第一区域和第二区域分别位于心轴的第一侧和第二侧。间隔膜可以包括诸如多晶硅或钨的导电材料。间隔膜可以可选地包括绝缘材料，例如二氧化硅，氮化硅或氮氧化硅。氧化膜形成为使得氧化物膜的第一区域和第二区域分别位于间隔膜的第一区域和第二区域上。氧化膜可以包括二氧化硅。第一蚀刻蚀刻掉氧化膜的第一区域和间隔膜的第一区域的一部分。第二蚀刻通过蚀刻掉间隔膜的剩余第一区域以及氧化膜的第二区域的一部分而形成方形间隔物，之后隔离膜的第二区域的顶表面和氧化膜的第二区域在基板上方大约相同的高度。第一和第二蚀刻可以通过反应离子蚀刻或化学下游蚀刻来实现。

82. 发明授权

US06180456B2 Triple polysilicon embedded NVRAM cell and method thereof 有权
标题翻译：三重多晶硅嵌入式NVRAM单元及其方法
公开(公告)号：US06180456B2
公开(公告)日：2001-01-30
申请号：US09251661
申请日：1999-02-17
申请人： Chung Hon Lam , Glen L. Miles , Jame Spiros Nakos , Christa R. Willets
发明人： Chung Hon Lam , Glen L. Miles , Jame Spiros Nakos , Christa R. Willets
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L21/823857 , H01L27/105 , H01L27/11546
摘要： A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.
摘要翻译：一种包括非易失性随机存取存储器（NVRAM）阵列的逻辑芯片及其制造方法。该芯片包括在三个多晶硅层中的一个或多个上具有栅极的器件。芯片逻辑使用正常的FET，阵列支持包括高压FET。逻辑和支持都是CMOS。芯片逻辑中的正常FET的栅极来自第三个最上面的多晶硅层。第三多晶硅层也用作高电压FET和阵列字线的掩模，两者都使用栅极的第二多晶硅层。第一多晶硅层仅用于电池浮动栅极。

83. 发明授权

US08860111B2 Phase change memory cell array with self-converged bottom electrode and method for manufacturing 有权
标题翻译：具有自会聚底电极的相变存储单元阵列及其制造方法
公开(公告)号：US08860111B2
公开(公告)日：2014-10-14
申请号：US13445194
申请日：2012-04-12
申请人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung Hon Lam , Matthew J. Breitwisch
IPC分类号： H01L27/108 , H01L27/24 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。最后，在存储器元件上形成位线以完成存储器单元。在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

84. 发明授权

US08324605B2 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US08324605B2
公开(公告)日：2012-12-04
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

85. 发明申请

US20120276688A1 METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 失效
标题翻译：用于形成用于PCRAM和自对准回退过程的自对准位线的方法
公开(公告)号：US20120276688A1
公开(公告)日：2012-11-01
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译：一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有上表面与牺牲材料的基座的上表面基本共面。牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。还提供了自对准的回蚀工艺。

86. 发明申请

US20120075925A1 PCRAM With Current Flowing Laterally Relative to Axis Defined By Electrodes 有权
标题翻译： PCRAM与当前电流相对于由电极定义的轴流动
公开(公告)号：US20120075925A1
公开(公告)日：2012-03-29
申请号：US13210020
申请日：2011-08-15
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： H01L45/06 , H01L45/1246 , H01L45/144 , H01L45/16
摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.
摘要翻译：改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。在另一示例中，相变结构围绕电介质结构。几种变化改善了相变结构和电极之间的接触。

87. 发明授权

US07983069B2 Write operations for phase-change-material memory 有权
标题翻译：相变材料存储器的写操作
公开(公告)号：US07983069B2
公开(公告)日：2011-07-19
申请号：US12146128
申请日：2008-06-25
申请人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
发明人： Louis L. C. Hsu , Brian L. Ji , Chung Hon Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0078 , G11C2213/79
摘要： Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.
摘要翻译：公开了用于相变材料（PCM）存储器件的改进的写操作技术。作为一个示例，在相变材料存储器单元中执行写入操作的方法，具有设置相位和与其相关联的复位阶段的存储器单元包括以下步骤。监视与存储器单元相关联的字线。当字线被激活时，启动对设置阶段的存储单元的写操作的执行。然后可以在设定阶段的有效数据可用时继续对设定阶段的存储单元的写入操作。当复位阶段的有效数据可用时，可以执行对复位阶段的存储单元的写操作。公开了其它改进的PCM写操作技术。

88. 发明授权

US07978509B2 Phase change memory with dual word lines and source lines and method of operating same 有权
标题翻译：具有双字线和源极线的相变存储器及其操作方法
公开(公告)号：US07978509B2
公开(公告)日：2011-07-12
申请号：US12759479
申请日：2010-04-13
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C8/08 , G11C8/14 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/74 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.
摘要翻译：相变存储器件包括存储单元，第一字线导体和第二字线导体，以及分别响应于第一和第二字线导体的第一和第二存取器件。控制电路被布置为仅使用第一字线导体访问存储器单元用于读取操作，以建立从位线到存储器单元到通过第一存取设备到源极线的电流路径，以及访问存储器单元以进行操作使用第一和第二接入设备来复位存储器单元以建立从位线到存储器单元到两条源极线的电流路径。

89. 发明申请

US20110121251A1 SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT 有权
标题翻译：单面罩相机更换记忆元件
公开(公告)号：US20110121251A1
公开(公告)日：2011-05-26
申请号：US12625855
申请日：2009-11-25
申请人： Matthew J. Breitwisch , Chung Hon Lam
发明人： Matthew J. Breitwisch , Chung Hon Lam
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：一种制造半导体结构内的相变存储元件的方法以及具有这样的半导体结构的方法，该方法包括蚀刻对底部电极的上表面的开口，所述开口由与形成的金属区域的高度相等的高度形成在半导体结构内的相同层的电介质层内，在开口内沉积共形膜并使保形膜凹陷以暴露底部电极的上表面，将相变材料沉积在开口内，使相变材料在内打开并在凹陷相变材料上形成顶部电极。

90. 发明授权

US07943420B1 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US07943420B1
公开(公告)日：2011-05-17
申请号：US12625855
申请日：2009-11-25
申请人： Matthew J. Breitwisch , Chung Hon Lam
发明人： Matthew J. Breitwisch , Chung Hon Lam
IPC分类号： H01L21/06
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：一种制造半导体结构内的相变存储元件的方法以及具有这样的半导体结构的方法，该方法包括蚀刻对底部电极的上表面的开口，所述开口由与形成的金属区域的高度相等的高度形成在半导体结构内的相同层的电介质层内，在开口内沉积共形膜并使保形膜凹陷以暴露底部电极的上表面，将相变材料沉积在开口内，使相变材料在内打开并在凹陷相变材料上形成顶部电极。

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