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81. 发明申请

US20120179879A1 MECHANISMS FOR EFFICIENT INTRA-DIE/INTRA-CHIP COLLECTIVE MESSAGING 有权
标题翻译：有效的内部/内部集体消息传递的机制
公开(公告)号：US20120179879A1
公开(公告)日：2012-07-12
申请号：US12986528
申请日：2011-01-07
申请人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
发明人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F15/167
摘要： Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.
摘要翻译：提供了具有单独的共享存储器一致性域的节点之间的有效模内集体处理的机制。集成电路管芯可以包括在集成电路管芯上实现的硬件集合单元。集成电路管芯上的多个核被分组成多个共享存储器相干域。多个共享存储器相干域中的每一个连接到集体单元，用于在多个共享存储器相干域之间执行集合操作。

82. 发明申请

US20120060016A1 Vector Loads from Scattered Memory Locations 审中-公开
标题翻译：矢量负载从分散的内存位置
公开(公告)号：US20120060016A1
公开(公告)日：2012-03-08
申请号：US12876432
申请日：2010-09-07
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30043
摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, a gather instruction is receive in a logic unit of a processor, the gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into a target vector register of the processor. A plurality of separate load instructions for loading the data from the plurality of addresses in the memory are automatically generated within the logic unit. The plurality of separate load instructions are sent, from the logic unit, to one or more load/store units of the processor. The data corresponding to the plurality of addresses is gathered in a buffer of the processor. The logic unit then writes data stored in the buffer to the target vector register.
摘要翻译：提供了执行分散加载操作的机构。利用这些机制，在处理器的逻辑单元中接收收集指令，所述收集指令指定要从中将数据加载到处理器的目标向量寄存器的存储器中的多个地址。在逻辑单元内自动生成用于从存储器中的多个地址加载数据的多个单独的加载指令。多个单独的加载指令从逻辑单元发送到处理器的一个或多个加载/存储单元。对应于多个地址的数据被收集在处理器的缓冲器中。然后，逻辑单元将存储在缓冲器中的数据写入目标向量寄存器。

83. 发明授权

US08103836B2 Snoop filtering system in a multiprocessor system 有权
标题翻译：多处理器系统中的Snoop过滤系统
公开(公告)号：US08103836B2
公开(公告)日：2012-01-24
申请号：US12126674
申请日：2008-05-23
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing unit, with each snoop filter unit comprising a plurality of devices for receiving asynchronous snoop requests from respective memory writing sources in the computing environment; and a point-to-point interconnect comprising communication links for directly connecting memory writing sources to corresponding receiving devices; and, a plurality of parallel operating filter devices coupled in one-to-one correspondence with each receiving device for processing snoop requests received thereat and one of forwarding requests or preventing forwarding of requests to its associated processing unit. Each of the plurality of parallel operating filter devices comprises parallel operating sub-filter elements, each simultaneously receiving an identical snoop request and implementing one or more different snoop filter algorithms for determining those snoop requests for data that are determined not cached locally at the associated processing unit and preventing forwarding of those requests to the processor unit. In this manner, a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持高速缓存一致性的系统和方法，每个单元具有与其可操作耦合的相关联的高速缓存存储器系统该系统包括多个互连的窥探过滤器单元，每个窥探过滤器单元对应于相应处理单元并与其通信，每个窥探过滤器单元包括用于在计算环境中从相应存储器写入源接收异步窥探请求的多个设备 ; 以及包括用于将存储器写入源直接连接到对应的接收设备的通信链路的点对点互连; 以及与每个接收设备一一对应地耦合的多个并行操作过滤器设备，用于处理在其上接收的窥探请求，并且转发请求之一或者阻止将请求转发到其相关联的处理单元。多个并行操作过滤器装置中的每一个包括并行操作子滤波器元件，每个并行操作子滤波器元件同时接收相同的窥探请求，并且实现一个或多个不同的窥探滤波器算法，用于确定对于在相关处理中本地未被缓存的数据被确定的窥探请求并且防止将这些请求转发到处理器单元。以这种方式，减少了转发到处理单元的多个窥探请求，从而增加了计算环境的性能。

84. 发明申请

US20110296421A1 METHOD AND APPARATUS FOR EFFICIENT INTER-THREAD SYNCHRONIZATION FOR HELPER THREADS 有权
标题翻译：用于帮助螺纹线的有效的线间同步的方法和装置
公开(公告)号：US20110296421A1
公开(公告)日：2011-12-01
申请号：US12787810
申请日：2010-05-26
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F9/52
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/4881 , G06F9/5022 , G06F9/52 , G06F9/542
摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.
摘要翻译：可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个硬件线程。可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

85. 发明申请

US20110173431A1 HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST RECONFIGURATION OF PERFORMANCE COUNTERS 失效
标题翻译：软件支持软件控制快速重新配置性能计数器
公开(公告)号：US20110173431A1
公开(公告)日：2011-07-14
申请号：US12684496
申请日：2010-01-08
申请人： Valentina Salapura , Robert W. Wisniewski
发明人： Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F1/24
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.
摘要翻译：对性能计数器的软件控制重新配置的硬件支持可以包括收集一个或多个所选活动的一个或多个计数的多个性能计数器。存储元件存储表示时间间隔的数据值，并且定时器元件基于数据值读取数据值并检测时间间隔的到期并生成信号。多个配置寄存器存储一组性能计数器配置。状态机从多个配置寄存器接收信号并选择配置寄存器，以重新配置一个或多个性能计数器。

86. 发明授权

US07877551B2 Programmable partitioning for high-performance coherence domains in a multiprocessor system 有权
标题翻译：用于多处理器系统中高性能相干域的可编程分区
公开(公告)号：US07877551B2
公开(公告)日：2011-01-25
申请号：US11768532
申请日：2007-06-26
申请人： Matthias A. Blumrich , Valentina Salapura
发明人： Matthias A. Blumrich , Valentina Salapura
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache, and the snoop units are provided for supporting cache coherency in the multiprocessor system. Each of the snoop units is connected to a respective one of the processing units and to all of the other snoop units. The multiprocessor computing system further includes a partitioning system for using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size processing groups. Preferably, when the processor units are partitioned into these processing groups, the partitioning system also configures the snoop units to maintain cache coherency within each of said groups.
摘要翻译：公开了一种多处理器计算系统和逻辑划分多处理器计算系统的方法。多处理器计算系统包括多个处理单元和多个窥探单元。每个处理单元包括本地高速缓存，并且提供窥探单元用于在多处理器系统中支持高速缓存一致性。每个窥探单元连接到相应的一个处理单元和所有其他窥探单元。多处理器计算系统还包括用于使用窥探单元将多个处理单元划分成多个独立的，存储器一致的可调整大小的处理组的分区系统。优选地，当处理器单元被划分成这些处理组时，分区系统还配置窥探单元以维持每个所述组内的高速缓存一致性。

87. 发明授权

US07836260B2 Low complexity speculative multithreading system based on unmodified microprocessor core 有权
标题翻译：基于未修改的微处理器核心的低复杂度推测性多线程系统
公开(公告)号：US07836260B2
公开(公告)日：2010-11-16
申请号：US12147914
申请日：2008-06-27
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

88. 发明授权

US07793038B2 System and method for programmable bank selection for banked memory subsystems 有权
标题翻译：用于存储存储器子系统的可编程存储体选择的系统和方法
公开(公告)号：US07793038B2
公开(公告)日：2010-09-07
申请号：US11768805
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F12/0804 , G06F12/0897 , Y02D10/13
摘要： A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.
摘要翻译：一种用于使得一个或多个处理器设备能够访问计算环境中的共享存储器的可编程存储器系统和方法，所述共享存储器包括具有用于存储数据的可寻址位置的一个或多个存储器存储结构。该系统包括：与相应的一个或多个处理器设备相关联的一个或多个第一逻辑设备，用于接收物理存储器地址信号的每个第一逻辑设备，并且可编程以在接收到预定地址位值时产生相应的存储器存储结构选择信号在选定的物理存储器地址位置; 以及响应于每个相应选择信号以产生用于选择用于处理器访问的存储器存储结构的地址信号的第二逻辑器件。因此，该系统使每个处理器设备能够分布在一个或多个存储器结构上的计算环境存储器存储访问。

89. 发明授权

US07761687B2 Ultrascalable petaflop parallel supercomputer 失效
标题翻译：超平面petaflop平行超级计算机
公开(公告)号：US07761687B2
公开(公告)日：2010-07-20
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

90. 发明授权

US07688931B2 Space and power efficient hybrid counters array 失效
标题翻译：空间和功率高效的混合计数器阵列
公开(公告)号：US07688931B2
公开(公告)日：2010-03-30
申请号：US12120416
申请日：2008-05-14
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

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