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81. 发明授权

US06845042B2 Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems 失效
标题翻译：非易失性半导体存储器，其制造方法，半导体集成电路和系统
公开(公告)号：US06845042B2
公开(公告)日：2005-01-18
申请号：US10359216
申请日：2003-02-06
申请人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
发明人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
IPC分类号： G11C16/00 , G06K17/00 , G06K19/077 , G11C11/34 , G11C14/00 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/82 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
摘要翻译：一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

82. 发明授权

US6151249A NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors 失效
标题翻译： NAND型EEPROM具有通常通过增强和耗尽晶体管耦合的位线和源极线
公开(公告)号：US6151249A
公开(公告)日：2000-11-21
申请号：US210288
申请日：1994-03-18
申请人： Riichiro Shirota , Masaki Momodomi
发明人： Riichiro Shirota , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.
摘要翻译：在包括多个NAND存储单元的EEPROM中，每个NAND存储单元通过将每个具有浮置栅极和控制栅极的存储单元彼此串联构成，第一选择晶体管分别耦合在每个相同位线和端子之间分别由多个存储单元中的两个NAND存储器单元构成的第一选择晶体管和分别耦合在另一侧的端子和源极线（SL）之间的第二选择晶体管，第一或第二选择晶体管由增强晶体管和耗尽型晶体管构成，彼此串联耦合，并且第一选择晶体管的耗尽晶体管和增强晶体管的布置与相同NAND存储器单元中的第二选择晶体管的布置相反。

83. 发明授权

US11211464B2 Normally-off nitride semiconductor transistor device 有权
公开(公告)号：US11211464B2
公开(公告)日：2021-12-28
申请号：US16705587
申请日：2019-12-06
申请人： Riichiro Shirota , Shinichiro Takatani
发明人： Riichiro Shirota , Shinichiro Takatani
IPC分类号： H01L29/423 , H01L29/205 , H01L29/417 , H01L29/06 , H01L29/778 , H01L29/20
摘要： A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor.

84. 发明申请

US20170221916A1 Flash Memory 有权
公开(公告)号：US20170221916A1
公开(公告)日：2017-08-03
申请号：US15412128
申请日：2017-01-23
申请人： Yukihiro Nagai , Riichiro Shirota , Hiroshi Watanabe , IMSolution Co., Ltd.
发明人： Te-Chang Tseng , Yukihiro Nagai , Riichiro Shirota , Hiroshi Watanabe
IPC分类号： H01L27/11568 , H01L29/423 , H01L29/51 , G11C16/04 , G11C16/14 , G11C16/26 , H01L29/16 , H01L27/11573 , G11C16/10
CPC分类号： H01L27/11568 , G11C5/063 , G11C16/0433 , G11C16/0466 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/16 , H01L29/42344 , H01L29/42348 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： A cheap and high performance 1.5 transistor-type flash memory highly compatible to external of memory region is provided. The flash memory has sacrifice film formed on substrate. U-shaped groove is formed on sacrifice film, where multiple insulating film is laminated. Multiple insulating film includes silicon nitride film as charge storage layer. Low resistive material is disposed on multiple insulating film to form control gate. Select gate is formed on insulating film on side of control gate in self-aligned manner. Semiconductor regions opposite in conductivity to substrate on both sides of adjoining control gate and select gate to form source and drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with adjoining control gate and select gate between source and drain. In MOS-type transistor with control gate, threshold voltage is changeable according to injection/emission of charge to silicon nitride as charge storage layer, and thus work as non-volatile memory.

85. 发明授权

US08405139B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
公开(公告)号：US08405139B2
公开(公告)日：2013-03-26
申请号：US13085884
申请日：2011-04-13
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

86. 发明申请

US20120168846A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20120168846A1
公开(公告)日：2012-07-05
申请号：US13421248
申请日：2012-03-15
申请人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11548 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L29/788
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

87. 发明申请

US20110272745A1 SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20110272745A1
公开(公告)日：2011-11-10
申请号：US13185930
申请日：2011-07-19
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L27/105
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

88. 发明申请

US20110108905A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110108905A1
公开(公告)日：2011-05-12
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

89. 发明授权

US07855918B2 Method for programming a memory structure 有权
标题翻译：用于编程存储器结构的方法
公开(公告)号：US07855918B2
公开(公告)日：2010-12-21
申请号：US12144645
申请日：2008-06-24
申请人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
发明人： Riichiro Shirota , Ching-Hsiang Hsu , Cheng-Jye Liu
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译：存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元。

90. 发明授权

US07791948B2 Channel carrier discharging in a NAND flash memory on an insulating substrate or layer 失效
标题翻译：通道载体在绝缘基板或层上的NAND闪速存储器中放电
公开(公告)号：US07791948B2
公开(公告)日：2010-09-07
申请号：US12165211
申请日：2008-06-30
申请人： Riichiro Shirota , Fumitaka Arai
发明人： Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/10
摘要： A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.
摘要翻译：半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中，器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。

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