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81. 发明授权

US5765035A Recorder buffer capable of detecting dependencies between accesses to a pair of caches 失效
标题翻译：重新排序缓冲器能够检测对一对缓存的访问之间的依赖关系
公开(公告)号：US5765035A
公开(公告)日：1998-06-09
申请号：US561075
申请日：1995-11-20
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F9/38 , G06F12/08 , G06F9/30 , G06F12/00
CPC分类号： G06F12/0848 , G06F9/3834 , G06F9/3861
摘要： A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage. The comparator circuits used to perform the comparison are configured to compare a field of address bits instead of the entire address, reducing the size while still maintaining accurate dependency checking by qualifying the resulting comparison signals with an indication that both addresses hit in the same storage location within the stack cache.
摘要翻译：提供了一种依赖性检查结构，其将从指令处理流水线的执行阶段执行的存储器访问与从解码级执行的存储器访问进行比较。解码级对堆栈高速缓存执行存储器访问，而执行级通过间接寻址将其访问（通过间接寻址形成的地址）执行到堆栈高速缓存和数据高速缓存。如果由执行级执行的读取存储器访问取决于由解码级执行的写存储器访问，则读存储器访问被停止，直到写存储器访问完成。如果由解码级执行的读取存储器访问取决于由执行级执行的写入存储器访问，则刷新与读取的存储器访问和后续指令相关联的指令。在一对缓存之间保持数据一致性，同时允许从解码级执行堆栈相对访问。用于执行比较的比较器电路被配置为比较地址位的字段而不是整个地址，减小大小，同时仍然通过将所得到的比较信号限定在相同存储位置中的两个地址的指示来保持精确的依赖性检查在堆栈缓存内。

82. 发明授权

US5748978A Byte queue divided into multiple subqueues for optimizing instruction selection logic 失效
标题翻译：字节队列分为多个子队列，用于优化指令选择逻辑
公开(公告)号：US5748978A
公开(公告)日：1998-05-05
申请号：US650940
申请日：1996-05-17
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F15/82
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： An apparatus for aligning variable byte length instructions to a plurality of issue positions is provided. The apparatus includes a byte queue divided into several subqueues. Each subqueue is maintained such that a first instruction in program order within the subqueue is identified by information stored in a first position within the subqueue, a second instruction in program order within the subqueue is identified by information stored in a second position within the subqueue, etc. When instructions from a subqueue are dispatched, remaining instructions within the subqueue are shifted such that the first of the remaining instructions (in program order) occupies the first position, etc. Instructions are shifted from subqueue to subqueue when each of the instructions within a particular subqueue have been dispatched. The information stored in one subqueue is shifted as a unit to another subqueue independent of the internal shifting of subqueue information. The subqueues are additionally configured to handle instructions which overflow from a first subqueue into a second subqueue. Information pertaining to the overflowing instructions is maintained in the last position within the first subqueue. The information is not shifted when other positions within the subqueue are shifted. In this manner, information regarding an overflowing instruction is again located in a limited number of positions.
摘要翻译：提供了一种用于将可变字节长度指令与多个发行位置对准的装置。该装置包括分为几个子队列的字节队列。维持每个子队列，使得在子队列内以程序顺序排列的第一指令通过存储在子队列内的第一位置的信息来识别，子队列内的程序顺序中的第二指令由存储在子队列内的第二位置的信息来识别，当发送来自子队列的指令时，子队列中的剩余指令被移位，使得剩余指令中的第一个（以程序顺序）占据第一位置等。当每个指令在已经调度了一个特定的子队列。存储在一个子队列中的信息作为一个单元移动到另一个子队列，而不依赖于子队列信息的内部移位。子队列另外配置为处理从第一子队列溢出到第二子队列的指令。关于溢出指令的信息被保持在第一子队列内的最后位置。当子队列中的其他位置移动时，信息不会移动。以这种方式，关于溢出指令的信息再次位于有限数量的位置。

83. 发明授权

US5345569A Apparatus and method for resolving dependencies among a plurality of instructions within a storage device 失效
标题翻译：用于解决存储装置内的多个指令之间的依赖性的装置和方法
公开(公告)号：US5345569A
公开(公告)日：1994-09-06
申请号：US764155
申请日：1991-09-20
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F5/10 , G06F5/12 , G06F7/74 , G06F9/38 , G06F9/06
CPC分类号： G06F7/74 , G06F5/12 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F2205/123
摘要： An apparatus and method for resolving data dependencies among a plurality of instructions within a storage device, such as a reorder buffer in a superscalar computing apparatus employing pipeline instruction processing. The storage device has a read pointer, indicating a most recently-stored instruction and has a write pointer, indicating a first-stored instruction of the plurality of instructions within the storage device.A compare-hit circuit generates a compare-hit signal upon each concurrence of the respective source indicator in a next-to-be-dispatched instruction with the destination indicator of an earlier-stored instruction within the storage device; a first enable circuit generates a first enable signal for a first packet of instructions defined by the read pointer and the write pointer; a first comparing circuit generates a hit-enable signal for each concurrence of the compare-hit signal and the first enable signal; a second enable circuit generates a second enable signal for a second packet of instructions defined by the read pointer and the hit-enable signal; and a second comparing circuit generates the output signal for each concurrence of the second enable signal and the hit-enable signal.
摘要翻译：一种用于解决存储装置内的多个指令之间的数据依赖性的装置和方法，例如采用流水线指令处理的超标量计算装置中的重排序缓冲器。存储装置具有指示最近存储的指令的读指针，并具有指示存储装置内的多个指令的第一存储指令的写指针。比较命中电路在下一个待分派指令中的相应源指示符的每次同时生成比较命中信号，其中存储设备内的先前存储的指令的目的地指示符; 第一使能电路产生用于由读指针和写指针定义的第一指令包的第一使能信号; 第一比较电路针对比较命中信号和第一使能信号的每次同步产生命中使能信号; 第二使能电路为由读指针和命中使能信号定义的第二指令分组生成第二使能信号; 并且第二比较电路产生用于第二使能信号和命中使能信号的每次同步的输出信号。

84. 发明授权

US09110656B2 Systems and methods for handling instructions of in-order and out-of-order execution queues 有权
标题翻译：用于处理有序和无序执行队列的指令的系统和方法
公开(公告)号：US09110656B2
公开(公告)日：2015-08-18
申请号：US13210566
申请日：2011-08-16
申请人： Thang M. Tran , Trinh Huy H. Nguyen
发明人： Thang M. Tran , Trinh Huy H. Nguyen
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30087 , G06F9/3814 , G06F9/3824 , G06F9/3838 , G06F9/3851 , G06F9/3891
摘要： A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The operands of the first instruction are determined to include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue. The first instruction is stored in a first entry of the second execution queue. A synchronization indicator corresponding to the first instruction in a second entry of the first execution queue is set immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue.
摘要翻译：一种处理器，被配置为向第一执行单元提供第一指令类型的指令，以及第二执行队列，被配置为向第二执行单元提供第二指令类型的指令。接收第二指令类型的第一指令。第一指令由解码/发布单元解码以确定第一指令的操作数。第一指令的操作数被确定为包括对存储在第一执行队列的第一条目中的第一指令类型的第二指令的依赖性。第一个指令存储在第二个执行队列的第一个条目中。与第一执行队列的第二条目中的第一指令相对应的同步指示符被设置为紧邻第一执行队列的第一条目，其指示第一指令被存储在另一个执行队列中。

85. 发明授权

US09092225B2 Systems and methods for reducing branch misprediction penalty 有权
标题翻译：减少分支误判处罚的制度和方法
公开(公告)号：US09092225B2
公开(公告)日：2015-07-28
申请号：US13362720
申请日：2012-01-31
申请人： Thang M. Tran , Michael B. Schinzler
发明人： Thang M. Tran , Michael B. Schinzler
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/381
摘要： In a processing system capable of single and multi-thread execution, a branch prediction unit can be configured to detect hard to predict branches and loop instructions. In a dual-threading (simultaneous multi-threading) configuration, one instruction queues (IQ) is used for each thread and instructions are alternately sent from each IQ to decode units. In single thread mode, the second IQ can be used to store the “not predicted path” of the hard-to-predict branch or the “fall-through” path of the loop. On mis-prediction, the mis-prediction penalty is reduced by getting the instructions from IQ instead of instruction cache.
摘要翻译：在能够进行单线程和多线程执行的处理系统中，分支预测单元可以被配置为检测难以预测分支和循环指令。在双线程（同时多线程）配置中，每个线程都使用一个指令队列（IQ），并将指令从每个IQ交替发送到解码单元。在单线程模式中，第二个IQ可用于存储难以预测的分支的“未预测路径”或循环的“直通”路径。在误预测中，通过从IQ而不是指令高速缓存获取指令来减少错误预测损失。

86. 发明授权

US09063747B2 Microprocessor systems and methods for a combined register file and checkpoint repair register 有权
标题翻译：组合寄存器文件和检查点修复寄存器的微处理器系统和方法
公开(公告)号：US09063747B2
公开(公告)日：2015-06-23
申请号：US13096282
申请日：2011-04-28
申请人： Thang M. Tran
发明人： Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/30116 , G06F9/3851
摘要： In a processor, a decode unit identifies instructions needing a checkpoint and enables selected checkpoints. A register file unit includes a plurality of architectural registers. A first set of checkpoint registers correspond to a first checkpoint. Each checkpoint register corresponds to a corresponding architectural register. A first set of indicators correspond to the first set of checkpoint registers to indicate whether the corresponding architectural register has been modified or is intended to be modified prior to enabling of the first checkpoint. A second set of indicators correspond to the first set of checkpoint registers and indicate whether the corresponding architectural register has been modified or is intended to be modified after enabling the first checkpoint.
摘要翻译：在处理器中，解码单元识别需要检查点的指令，并启用选定的检查点。寄存器文件单元包括多个架构寄存器。第一组检查点寄存器对应于第一个检查点。每个检查点寄存器对应于相应的架构寄存器。第一组指示符对应于第一组检查点寄存器，以指示对应的体系结构寄存器是否已经被修改，或者是在第一检查点启用之前被修改。第二组指示符对应于第一组检查点寄存器，并且指示相应的体系结构寄存器是否已被修改或在启用第一检查点之后被修改。

87. 发明申请

US20140095784A1 Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance 有权
标题翻译：利用事务后备缓冲区入口号来提高处理器性能的技术
公开(公告)号：US20140095784A1
公开(公告)日：2014-04-03
申请号：US13630346
申请日：2012-09-28
申请人： Thang M. Tran , Edmund J. Gieske
发明人： Thang M. Tran , Edmund J. Gieske
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A technique for operating a processor includes translating, using an associated transaction lookaside buffer, a first virtual address into a first physical address through a first entry number in the transaction lookaside buffer. The technique also includes translating, using the transaction lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
摘要翻译：用于操作处理器的技术包括通过事务后备缓冲器中的第一条目号码将使用相关联的事务后备缓冲器的第一虚拟地址翻译成第一物理地址。该技术还包括通过翻译后备缓冲器中的第二条目号码将使用事务后备缓冲器的第二虚拟地址翻译成第二物理地址。该技术还包括响应于第一入口号与第二入口号相同，确定第一和第二虚拟地址指向存储器中相同的物理地址并引用相同的数据。

88. 发明申请

US20130290639A1 APPARATUS AND METHOD FOR MEMORY COPY AT A PROCESSOR 有权
标题翻译：用于处理器的存储器复制的装置和方法
公开(公告)号：US20130290639A1
公开(公告)日：2013-10-31
申请号：US13455800
申请日：2012-04-25
申请人： Thang M. Tran , James Yang
发明人： Thang M. Tran , James Yang
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F9/30032 , G06F9/30043 , G06F9/3838 , G06F9/384 , G06F12/0897
摘要： A processor uses a dedicated buffer to reduce the amount of time needed to execute memory copy operations. For each load instruction associated with the memory copy operation, the processor copies the load data from memory to the dedicated buffer. For each store operation associated with the memory copy operation, the processor retrieves the store data from the dedicated buffer and transfers it to memory. The dedicated buffer is separate from a register file and caches of the processor, so that each load operation associated with a memory copy operation does not have to wait for data to be loaded from memory to the register file. Similarly, each store operation associated with a memory copy operation does not have to wait for data to be transferred from the register file to memory.
摘要翻译：处理器使用专用缓冲器来减少执行内存复制操作所需的时间。对于与存储器复制操作相关联的每个加载指令，处理器将负载数据从存储器复制到专用缓冲区。对于与存储器复制操作相关联的每个存储操作，处理器从专用缓冲器检索存储数据并将其传送到存储器。专用缓冲器与寄存器文件和处理器的高速缓存分开，使得与存储器复制操作相关联的每个加载操作不必等待数据从存储器加载到寄存器文件。类似地，与存储器复制操作相关联的每个存储操作不必等待数据从寄存器文件传送到存储器。

89. 发明申请

US20130212358A1 DATA PROCESSING SYSTEM WITH LATENCY TOLERANCE EXECUTION 有权
标题翻译：具有延期执行的数据处理系统
公开(公告)号：US20130212358A1
公开(公告)日：2013-08-15
申请号：US13397452
申请日：2012-02-15
申请人： Thang M. Tran , Trinh Huy Nguyen
发明人： Thang M. Tran , Trinh Huy Nguyen
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
CPC分类号： G06F9/3855 , G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/3851
摘要： A data processing system comprises a processor unit that includes an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned, a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result, and a forward indicator to indicate that the status bit can be forwarded to an execution queue of an instruction pointed to that is waiting to receive the status bit.
摘要翻译：一种数据处理系统，包括：处理器单元，其包括指令解码/发布单元，该指令解码/发布单元包括具有条目的重新排序缓冲器，所述条目包括指示分配了重新排序缓冲器条目的指令的执行队列位置的执行队列标签，结果有效指示符，以指示相应的指令已经执行了状态位有效结果，以及前向指示符，以指示状态位可以被转发到指示正在等待接收状态位的指令的执行队列。

90. 发明授权

US08458447B2 Branch target buffer addressing in a data processor 有权
标题翻译：在数据处理器中分支目标缓冲区寻址
公开(公告)号：US08458447B2
公开(公告)日：2013-06-04
申请号：US13162835
申请日：2011-06-17
申请人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
发明人： Thang M. Tran , Edmund J. Gieske , Michael B. Schinzler
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3806
摘要： A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.
摘要翻译：数据处理器包括具有以方式分组的多个BTB条目的分支目标缓冲器（BTB）。其中一种方式的BTB条目包括一个短标签地址，而另一种方式的BTB条目包括一个完整的标签地址。

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