会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 86. 发明授权
    • Redundancy circuit capable of reducing time for redundancy discrimination
    • 冗余电路能够减少冗余辨别的时间
    • US07643361B2
    • 2010-01-05
    • US11959414
    • 2007-12-18
    • Hyuck Soo Yoon
    • Hyuck Soo Yoon
    • G11C11/00
    • G11C29/84
    • A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row address signals to a plurality of fuse address signals; and a redundancy control signal generating unit for providing a redundancy control signal by controlling an output signal path of the comparison signal receiving unit in response to a signal level of a row address enable signal. The comparison signal receiving unit receives the plurality of the comparison signals and the fuse enable signal while the row address enable signal is activated.
    • 半导体存储装置中的冗余电路包括:比较信号接收单元,用于并行地接收多个比较信号和熔丝使能信号,其中通过将多个行地址信号与多个熔丝地址信号进行比较来产生比较信号 ; 以及冗余控制信号生成单元,用于响应于行地址使能信号的信号电平,控制比较信号接收单元的输出信号路径来提供冗余控制信号。 当行地址使能信号被激活时,比较信号接收单元接收多个比较信号和熔丝使能信号。