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81. 发明授权

US06549484B2 Semiconductor device 有权
公开(公告)号：US06549484B2
公开(公告)日：2003-04-15
申请号：US09964669
申请日：2001-09-28
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

82. 发明授权

US06498762B2 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06498762B2
公开(公告)日：2002-12-24
申请号：US10040452
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

83. 发明授权

US06407963B1 Semiconductor memory device of DDR configuration having improvement in glitch immunity 有权
标题翻译：具有提高毛刺抗扰性的DDR配置的半导体存储器件
公开(公告)号：US06407963B1
公开(公告)日：2002-06-18
申请号：US09689664
申请日：2000-10-13
申请人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
发明人： Takahiro Sonoda , Takeshi Sakata , Sadayuki Morita , Yoshinobu Nakagome , Haruko Tadokoro , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C8/12
摘要： A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.
摘要翻译： DDR配置的半导体存储器件提高了毛刺抗扰性，并且提供了使用的便利。它是一种动态类型的RAM，其内部电路与时钟信号同步地被控制; 提供了一种输入电路，其中在写入操作时输入的第二时钟信号用于将响应于该信号串行输入的多个写数据写入多个第一锁存电路，并且所述第一时钟信号用于采取写入第一锁存电路的数据进入第二锁存电路，以将它们传送到输入/输出数据总线; 提供逻辑电路，以根据第一时钟信号和第二时钟信号的逻辑屏蔽在第二时钟信号结束时产生的任何噪声，并产生第三时钟信号并将其提供给第一锁存电路其将写数据输出到至少第二锁存电路的输入。

84. 发明授权

US06341088B2 Dynamic random access memory in switch MOSFETs between sense amplifiers and bit lines 有权
标题翻译：读出放大器和位线之间的开关MOSFET中的动态随机存取存储器
公开(公告)号：US06341088B2
公开(公告)日：2002-01-22
申请号：US09750038
申请日：2000-12-29
申请人： Tatsuya Sakamoto , Osamu Nagashima , Riichiro Takemura
发明人： Tatsuya Sakamoto , Osamu Nagashima , Riichiro Takemura
IPC分类号： G11C700
CPC分类号： G11C11/4097 , G11C7/06 , G11C7/18 , G11C11/4091
摘要： Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.
摘要翻译：开关MOSFET插在布置在动态RAM中的读出放大器和互补位线之间。在通过从所选择的多个动态存储器单元中选择字线的操作来读出信号电压之后，根据各个存储信息到多对互补位线，开关MOSFET的开关控制信号从选择水平到预定的中间水平。这将导通开关MOSFET，从而根据读出放大器的放大操作将感测节点设置到一个电平。通过放大运算产生的放大信号响应于列选择信号通过列选择电路发送到输入/输出线，并且响应于列选择电路的选择操作，开关控制信号返回到选择电平。

85. 发明授权

US06240035B1 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06240035B1
公开(公告)日：2001-05-29
申请号：US09302437
申请日：1999-04-30
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

86. 发明授权

US06201728B1 Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device 有权
标题翻译：动态RAM，半导体存储器件和半导体集成电路器件
公开(公告)号：US06201728B1
公开(公告)日：2001-03-13
申请号：US09101009
申请日：1999-02-08
申请人： Seiji Narui , Osamu Nagashima , Masatoshi Hasegawa , Hiroki Fujisawa , Shinichi Miyatake , Tsuyuki Suzuki , Yasunobu Aoki , Tsutom Takahashi , Kazuhiko Kajigaya
发明人： Seiji Narui , Osamu Nagashima , Masatoshi Hasegawa , Hiroki Fujisawa , Shinichi Miyatake , Tsuyuki Suzuki , Yasunobu Aoki , Tsutom Takahashi , Kazuhiko Kajigaya
IPC分类号： G11C1124
CPC分类号： G11C11/4091 , G11C7/065 , H01L27/10805
摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.
摘要翻译：产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。第一电压作为其高级侧的工作电压被提供给读出放大器。产生相对于电路接地电位具有预定差异的第二内部电压。第二电压作为低电平侧的工作电压提供给读出放大器。通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。

87. 发明授权

US5615145A Semiconductor memory with ferroelectric capacitors 失效
标题翻译：半导体存储器与铁电电容器
公开(公告)号：US5615145A
公开(公告)日：1997-03-25
申请号：US580090
申请日：1995-12-20
申请人： Kan Takeuchi , Katsumi Matsuno , Kazuhiko Kajiyama , Osamu Nagashima , Masatoshi Hasegawa
发明人： Kan Takeuchi , Katsumi Matsuno , Kazuhiko Kajiyama , Osamu Nagashima , Masatoshi Hasegawa
IPC分类号： G11C11/22 , G11C14/00 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： G11C11/22
摘要： A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.
摘要翻译：一种半导体存储器，包括多个存储单元，每个存储单元均具有串联连接的第一和第二电容器，以及源极或漏极连接到第一和第二电容器之间的节点的场效应晶体管。存储单元布置在位线和字线的交点处，从而形成矩阵。每个存储单元的第一电容器是使用铁电材料作为绝缘膜的铁电电容器。当存储器以第一模式操作时，每个存储单元的第一电容器的平板电极被保持在第一电位，并且当存储器在第二模式下操作时，第一电容器的平板电极被保持在第二电位。第一个潜力与第二个潜力不同。

88. 发明授权

US4947373A Dynamic ram 失效
标题翻译：动态ram
公开(公告)号：US4947373A
公开(公告)日：1990-08-07
申请号：US134355
申请日：1987-12-17
申请人： Yasunori Yamaguchi , Katsuyuki Sato , Jun Mitake , Hitoshi Kawaguchi , Masahiro Yoshida , Terutaka Okada , Makoto Morino , Tetsuya Saeki , Yosuke Yukawa , Osamu Nagashima
发明人： Yasunori Yamaguchi , Katsuyuki Sato , Jun Mitake , Hitoshi Kawaguchi , Masahiro Yoshida , Terutaka Okada , Makoto Morino , Tetsuya Saeki , Yosuke Yukawa , Osamu Nagashima
IPC分类号： G11C11/4096
CPC分类号： G11C11/4096
摘要： A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.
摘要翻译：半导体存储器设置有第一存储单元组，第二存储单元组，用于保持与第一存储单元组相关的信息的串行输出操作的第一寄存器，用于保持与第一存储单元组相关的信息的串行输出操作的第二寄存器第二存储单元组和用于将与第一或第二存储单元组相关的信息传送到第一或第二串行输出寄存器的传送装置。通过这种布置，当传送到第一串行输出寄存器的信息正在从其串行输出时，信息可以由传送装置同时传送到第二串行输出寄存器。

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