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81. 发明申请

US20100012990A1 MOSFETS INCLUDING CRYSTALLINE SACRIFICIAL STRUCTURES 审中-公开
标题翻译：包括晶体非线性结构的MOSFET
公开(公告)号：US20100012990A1
公开(公告)日：2010-01-21
申请号：US12566389
申请日：2009-09-24
申请人： MIN-SANG KIM , CHANG-WOO OH , DONG-WON KIM , KYOUNG-HWAN YEO , SUNG-MIN KIM
发明人： MIN-SANG KIM , CHANG-WOO OH , DONG-WON KIM , KYOUNG-HWAN YEO , SUNG-MIN KIM
IPC分类号： H01L29/78
CPC分类号： H01L29/0653 , H01L29/0649 , H01L29/6659
摘要： A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET.
摘要翻译：亚微米沟道长度MOSFET包括在MOSFET的衬底中的无缝外延沟道区域和在无缝外延沟道区下面的掩埋器件隔离层。在根据本发明的一些实施例中，掩埋器件隔离层包括在无缝外延沟道的中心部分下方的掩埋器件隔离层，并且不存在于MOSFET的源极/漏极区域的侧壁。

82. 发明授权

US07605025B2 Methods of forming MOSFETS using crystalline sacrificial structures 有权
标题翻译：使用晶体牺牲结构形成MOSFET的方法
公开(公告)号：US07605025B2
公开(公告)日：2009-10-20
申请号：US11050557
申请日：2005-02-03
申请人： Min-sang Kim , Chang-woo Oh , Dong-won Kim , Kyoung-hwan Yeo , Sung-min Kim
发明人： Min-sang Kim , Chang-woo Oh , Dong-won Kim , Kyoung-hwan Yeo , Sung-min Kim
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/0653 , H01L29/0649 , H01L29/6659
摘要： A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.
摘要翻译：可以通过在牺牲晶体结构的上表面上和衬底上生长外延半导体层以形成掩埋牺牲结构来形成金属氧化物半导体场效应晶体管（MOSFET）。可以去除掩埋的牺牲结构以形成空穴而不是埋入的牺牲结构，并且可以在空隙中形成器件隔离层。

83. 发明申请

US20090197383A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090197383A1
公开(公告)日：2009-08-06
申请号：US12353398
申请日：2009-01-14
申请人： Sung-Min Kim , Min-Sang Kim , Keun-Hwi Cho , Ji-Myoung Lee
发明人： Sung-Min Kim , Min-Sang Kim , Keun-Hwi Cho , Ji-Myoung Lee
IPC分类号： H01L21/336 , H01L21/335
CPC分类号： H01L21/823425 , H01L21/28123 , H01L21/823437 , H01L21/823468 , H01L29/42376 , H01L29/66659 , H01L29/7835
摘要： A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.
摘要翻译：制造半导体器件的方法形成微尺寸栅极，并减轻短沟道效应。该方法包括在衬底上形成栅极的回拉工艺。该方法还包括在栅极上形成相对于栅极彼此不对称的内部和外部间隔物，以及在栅极的相对侧上在衬底中形成接合区域的间隔物。特别地，内部和外部间隔件形成在栅极的相对侧上，以便在栅极的底部具有不同的厚度。通过在形成间隔物之前和之后掺杂衬底来形成内部和外部结区域。因此，内部和外部连接区域分别在内部和外部间隔件下方具有延伸区域，并且延伸区域具有不同的长度。

84. 发明申请

US20090057761A1 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20090057761A1
公开(公告)日：2009-03-05
申请号：US12230571
申请日：2008-09-02
申请人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
发明人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/7856 , H01L29/4925 , H01L29/4958 , H01L29/66795
摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.
摘要翻译：提供FinFET及其制造方法。 FinFET可以包括至少一个有源鳍片，至少一个栅极绝缘层图案，第一电极图案，第二电极图案和至少一对源极/漏极扩展区域。所述至少一个活性翅片可以形成在基底上。至少一个栅极绝缘层图案可以形成在至少一个活性鳍上。第一电极图案可以形成在至少一个栅极绝缘层图案上。此外，第一电极图案可以与至少一个活性鳍相交。第二电极图案可以形成在第一电极图案上。此外，第二电极图案可以具有大于第一电极图案的宽度的宽度。至少一对源极/漏极扩展区域可以形成在第一电极图案的两侧上的至少一个有源鳍片的表面上。因此，FinFET可能具有改进的容量和减小的GIDL电流。

85. 发明申请

US20080293827A1 Temperature and Ph Sensitive Block Copolymer and Polymeric Hydrogels Using the Same 有权
标题翻译：温度和Ph敏感嵌段共聚物和聚合物水凝胶使用它
公开(公告)号：US20080293827A1
公开(公告)日：2008-11-27
申请号：US11815960
申请日：2006-03-31
申请人： Doo Sung Lee , Min Sang Kim , Je Sun You , Huynh Dai Phu , Bong Sup Kim , Minh Khanh Nguyen
发明人： Doo Sung Lee , Min Sang Kim , Je Sun You , Huynh Dai Phu , Bong Sup Kim , Minh Khanh Nguyen
IPC分类号： A61K47/32 , C08L71/00 , C08G65/08
CPC分类号： C08G65/33306 , C08G65/331 , C08G65/3322 , C08G65/3324 , C08G73/028 , C08G81/00 , C08L53/00 , C08L67/00 , C08L71/02 , C08L2203/02 , C08L2205/05 , C08L2666/02 , C08L2666/18
摘要： Disclosed is a block copolymer formed by coupling the following components with each other: (a) a copolymer (A) of a polyethylene glycol (PEG) type compound with a biodegradable polymer; and (b) at least one oligomer (B) selected from the group consisting of poly(β-amino ester) and poly(amido amine). A method for preparing the same block copolymer, and a polymeric hydrogel type drug composition comprising the temperature and pH-sensitive block copolymer and a physiologically active substance that can be encapsulated with the block copolymer are also disclosed. The multiblock copolymer is obtained by copolymerization of a pH-sensitive poly(β-amino ester) and/or poly(amido amine) type oligomer, a hydrophilic and temperature-sensitive polyethylene glycol type compound and a hydrophobic and biodegradable polymer. Therefore, the block copolymer can form a polymeric hydrogel structure due to its amphiphilicity resulting from the combination of a hydrophilic group and a hydrophobic group in the copolymer and ionization characteristics depending on pH variations, and thus can be used as a drug carrier for target-directed drug delivery depending on pH variations in the body.
摘要翻译：公开了通过将以下组分彼此偶联而形成的嵌段共聚物：（a）聚乙二醇（PEG）型化合物与可生物降解聚合物的共聚物（A）和（b）至少一种选自聚（β-氨基酯）和聚（酰氨基胺）的低聚物（B）。还公开了制备相同嵌段共聚物的方法和包含温度和pH敏感性嵌段共聚物的聚合物水凝胶型药物组合物和可以用嵌段共聚物包封的生理活性物质。多嵌段共聚物通过pH敏感的聚（β-氨基酯）和/或聚（酰氨基胺）型低聚物，亲水和温度敏感的聚乙二醇型化合物和疏水和可生物降解的聚合物共聚获得。因此，嵌段共聚物由于其在共聚物中的亲水基团和疏水基团的组合引起的两亲性而形成聚合物水凝胶结构，并且根据pH变化而具有电离特性，因此可以用作靶向的药物载体，定向药物递送取决于体内的pH变化。

86. 发明申请

US20080219048A1 Multibit electro-mechanical memory device and method of manufacturing the same 有权
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US20080219048A1
公开(公告)日：2008-09-11
申请号：US12074645
申请日：2008-03-05
申请人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
发明人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
IPC分类号： H01H11/00 , G11C11/50
CPC分类号： H01L27/10 , G11C11/50 , H01H59/0009 , H01L27/105 , H01L27/115 , Y10T29/49105
摘要： A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad electrode isolated from a sidewall of the trap site and the lower word line and connected to the bit line, a cantilever electrode suspended over a lower void in an upper part of the trap site, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a contact part for concentrating a charge induced from the cantilever electrode thereon in response to the charge applied from the lower word line and the trap site, the contact part protruding from an end part of the cantilever electrode, and an upper word line formed with an upper void on the cantilever electrode.
摘要翻译：提供了能够提高存储器件集成度的多位机电存储器件及其制造方法。存储器件包括衬底，衬底上的位线; 与位线隔离的下部字线和陷阱位置，从陷阱位置的侧壁和下部字线隔离并连接到位线的焊盘电极，悬挂在上部的下部空隙上的悬臂电极并且通过施加到下字线的电荷引起的电场，连接到焊盘电极并且在垂直于第一和第二方向的第三方向上弯曲，用于聚集从悬臂电极引起的电荷的接触部分响应于从下文字线和陷阱位置施加的电荷，从悬臂电极的端部突出的接触部分和在悬臂电极上形成有上部空隙的上字线。

87. 发明申请

US20080099849A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A MULTI-CHANNEL TYPE MOS TRANSISTOR 有权
标题翻译：制造具有多通道型MOS晶体管的半导体器件的制造方法
公开(公告)号：US20080099849A1
公开(公告)日：2008-05-01
申请号：US11876613
申请日：2007-10-22
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.
摘要翻译：在制造半导体器件的方法中，在衬底上形成有源沟道图案。有源沟道图案包括彼此交替堆叠的初步栅极图案和单晶硅图案。源极/漏极层形成在有源沟道图案的侧壁上。在有源沟道图案和源极/漏极层上形成包括栅极沟槽的掩模图案结构。选择性地蚀刻图案以形成隧道。然后用栅电极填充栅极沟槽。栅电极围绕有源沟道图案。栅电极从有源沟道图案突出。然后去除掩模图案结构。将杂质注入源/漏区以形成源/漏区。在源极/漏极区域上进行硅化处理以形成金属硅化物层，从而完成具有MOS晶体管的半导体器件。

88. 发明申请

US20080029811A1 Vertical Twin-Channel Transistors and Methods of Fabricating the Same 审中-公开
标题翻译：垂直双通道晶体管及其制造方法
公开(公告)号：US20080029811A1
公开(公告)日：2008-02-07
申请号：US11687079
申请日：2007-03-16
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim , Hye-Jin Cho
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/513 , H01L29/66666 , H01L29/7831
摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.
摘要翻译：晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。栅电极设置在第一和第二栅极绝缘体之间。第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。

89. 发明申请

US20070048938A1 Method of manufacturing MOS transistor with multiple channel structure 审中-公开
标题翻译：制造具有多通道结构的MOS晶体管的方法
公开(公告)号：US20070048938A1
公开(公告)日：2007-03-01
申请号：US11431626
申请日：2006-05-10
申请人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim , Yong-lack Choi
发明人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim , Yong-lack Choi
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795
摘要： A method of manufacturing a MOS transistor with a multiple channel structure prevents damage to and loss of material of a channel region. The method includes: forming a stacked structure including a plurality of first material layers and a plurality of second material layers that have different etching selectivities and are alternately stacked on a semiconductor substrate; forming an active mask on a portion of the stacked structure, the active mask defining an active region; etching regions of the stacked structure to expose sidewalls of the stacked structure; forming a plurality of tunnels by selectively removing the first material layer between the exposed sidewalls of the stacked structure; removing the active mask; and forming a gate electrode on the active region to fill the plurality of tunnels.
摘要翻译：制造具有多通道结构的MOS晶体管的方法防止了沟道区的材料损坏和损失。该方法包括：形成包括多个第一材料层和多个具有不同蚀刻选择性的第二材料层并交替堆叠在半导体衬底上的层叠结构; 在所述堆叠结构的一部分上形成有源掩模，所述有源掩模限定有源区; 蚀刻所述堆叠结构的区域以暴露所述堆叠结构的侧壁; 通过选择性地去除所述堆叠结构的暴露的侧壁之间的第一材料层来形成多个隧道; 去除活性面膜; 以及在所述有源区上形成栅电极以填充所述多个隧道。

90. 发明申请

US20060175669A1 Semiconductor device including FinFET having metal gate electrode and fabricating method thereof 审中-公开
标题翻译：包括具有金属栅电极的FinFET的半导体器件及其制造方法
公开(公告)号：US20060175669A1
公开(公告)日：2006-08-10
申请号：US11339126
申请日：2006-01-25
申请人： Sung-min Kim , Dong-won Kim , Min-sang Kim , Eun-jung Yun
发明人： Sung-min Kim , Dong-won Kim , Min-sang Kim , Eun-jung Yun
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66545 , H01L29/66795
摘要： Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.
摘要翻译：提供了包括具有金属栅极的FinFET的半导体器件及其制造方法。半导体器件包括：形成在半导体衬底中并从半导体衬底的表面突出的有源区; 翅片，其包括由有源区域的表面形成的第一和第二突起，并且基于形成在有源区域中的中心沟槽并且使用第一和第二突起的上表面和侧面作为沟道区域彼此平行; 形成在包括所述鳍片的所述有源区域上的栅极绝缘层; 形成在所述栅极绝缘层上的金属栅电极; 形成在所述金属栅电极的侧壁上的栅极间隔; 以及在金属栅电极的两侧旁边的有源区域中形成的源极和漏极。这里，金属栅电极包括与栅极间隔物和栅极绝缘层接触的阻挡层和形成在阻挡层上的金属层。

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