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81. 发明授权

US06969895B2 MRAM cell with flat topography and controlled bit line to free layer distance and method of manufacture 有权
公开(公告)号：US06969895B2
公开(公告)日：2005-11-29
申请号：US10732013
申请日：2003-12-10
申请人： Cherng-Chyi Han , Liubo Hong
发明人： Cherng-Chyi Han , Liubo Hong
IPC分类号： H01F10/32 , G11C11/14 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L29/82 , H01L31/062 , H01L43/08 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

82. 发明申请

US20050260772A1 A METHOD OF FORMING A MAGNETIC TUNNELING JUNCTION (MTJ) MRAM DEVICE AND A TUNNELING MAGNETORESISTIVE (TMR) READ HEAD 有权
标题翻译：形成磁性隧道结（MTJ）MRAM器件和隧道磁阻（TMR）读取头的方法
公开(公告)号：US20050260772A1
公开(公告)日：2005-11-24
申请号：US10849310
申请日：2004-05-19
申请人： Cheng Horng , Liubo Hong , Ru-Ying Tong , Yu-Hsia Chen
发明人： Cheng Horng , Liubo Hong , Ru-Ying Tong , Yu-Hsia Chen
IPC分类号： G11B5/39 , G11C11/15 , G11C11/16 , H01F10/30 , H01F10/32 , H01F41/18 , H01F41/30 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L43/10 , H01L43/12 , H01L21/00
CPC分类号： B82Y25/00 , B82Y40/00 , G11C11/161 , H01F10/30 , H01F10/3272 , H01F10/3295 , H01F41/307 , H01L43/08 , H01L43/12
摘要： An MTJ (magnetic tunneling junction) device particularly suitable for use as an MRAM (magnetic random access memory) or a tunneling magnetoresistive (TMR) read sensor, is formed on a seed layer which allows the tunneling barrier layer to be ultra-thin, smooth, and to have a high breakdown voltage. The seed layer is a layer of NiCr which is formed on a sputter-etched layer of Ta. The tunneling barrier layer for the MRAM is formed from a thin layer of Al which is radically oxidized (ROX), in-situ, to form the layer with characteristics described above. The tunneling barrier layer for the read sensor formed from a thin layer of Al or a HfAl bilayer which is naturally oxidized (NOX), in-situ, to form the barrier layer. The resulting device has generally improved performance characteristics in terms of GMR ratio and junction resistance.
摘要翻译：特别适合用作MRAM（磁性随机存取存储器）或隧道磁阻（TMR）读取传感器的MTJ（磁性隧道结）装置形成在种子层上，允许隧穿势垒层超薄，平滑，并具有高的击穿电压。种子层是形成在Ta的溅射蚀刻层上的NiCr层。用于MRAM的隧道势垒层由Al的薄层形成，其被自由基氧化（ROX），原位形成具有上述特征的层。用于读取传感器的隧道势垒层由Al或HfAl双层的薄层形成，其被天然氧化（NOX）原位形成以形成阻挡层。所得到的器件在GMR比和结电阻方面基本上具有改进的性能特征。

83. 发明申请

US20050254293A1 Novel structure/method to fabricate a high-performance magnetic tunneling junction MRAM 失效
标题翻译：制造高性能磁隧道结MRAM的新型结构/方法
公开(公告)号：US20050254293A1
公开(公告)日：2005-11-17
申请号：US10844171
申请日：2004-05-12
申请人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
发明人： Cheng Horng , Mao-Min Chen , Liubo Hong , Ru-Ying Tong
IPC分类号： G11C11/00 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08 , Y10S977/934 , Y10S977/935
摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.
摘要翻译：在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。作为溅射蚀刻的结果，Ta层具有光滑的表面，并且光滑的表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层），其中具有超薄，光滑，且具有较高的击穿电压。在Ta的溅射蚀刻层上形成NiCr种子层。在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。

84. 发明申请

US20050248980A1 MRAM cell with flat topography and controlled bit line to free layer distance and method of manufacture 有权
标题翻译：具有平坦地形和受控位线的自由层距离和制造方法的MRAM单元
公开(公告)号：US20050248980A1
公开(公告)日：2005-11-10
申请号：US11179252
申请日：2005-07-12
申请人： Cherng-Chyi Han , Liubo Hong
发明人： Cherng-Chyi Han , Liubo Hong
IPC分类号： H01F10/32 , G11C11/14 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L29/82 , H01L31/062 , H01L43/08 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.
摘要翻译：一种用于形成MRAM单元结构的方法，其中单元的形貌基本上是平坦的，并且位线和无磁性层，字线和无磁性层或字线以及位线和无磁层之间的距离是精确和良好的控制。该方法包括形成MTJ膜堆叠，在其上形成封盖层和牺牲层。堆叠通过常规方式图案化，然后被由CMP稀疏以暴露牺牲层的剩余部分的绝缘层覆盖。可以通过蚀刻工艺精确地去除牺牲层的剩余部分，仅留下孔尺寸的覆盖层以将位线与无磁性层和封盖层分离。位线和绝缘层的绝缘层以同样精确和受控的方式将自由层与字线分开。

85. 发明授权

US06361661B1 Hybrid coil design for ionized deposition 失效
公开(公告)号：US06361661B1
公开(公告)日：2002-03-26
申请号：US08857944
申请日：1997-05-16
申请人： Liubo Hong
发明人： Liubo Hong
IPC分类号： C23C1434
摘要： A sputtering hybrid coil for a plasma chamber in a semiconductor fabrication has an enhanced sputtering surface and an internal coolant carrying channel thermally coupled to the sputtering surface to cool the sputtering surface and the coil.

86. 发明授权

US06178070B1 Magnetic write head and method for making same 有权
标题翻译：磁写头及其制作方法
公开(公告)号：US06178070B1
公开(公告)日：2001-01-23
申请号：US09248572
申请日：1999-02-11
申请人： Liubo Hong , Zhupei Shi
发明人： Liubo Hong , Zhupei Shi
IPC分类号： G11B5147
CPC分类号： G11B5/3967 , G11B5/313
摘要： A magnetoresistive device for recording data includes a first pole connected to a second pole that is above the first pole. Above the first pole is a first conductive coil imbedded in a first insulation material, with at least a portion of the first conductive layer disposed below all of the second pole. The first and second poles have a first and second pole tip portion, respectively, between which is defined a write gap. A first pole pedestal, connected to the first pole at the first pole tip portion, and a second pole pedestal, connected to the second pole at the second pole tip portion, can be located between the first and second poles. Also, additional conductive coils can be included above the first conductive coil.
摘要翻译：用于记录数据的磁阻装置包括连接到第一极上方的第二极的第一极。第一极上方是嵌入第一绝缘材料中的第一导电线圈，第一导电层的至少一部分设置在所有第二极下方。第一和第二极分别具有第一和第二极尖部分，其间限定有写入间隙。与第一极尖部分的第一极连接的第一极基座和与第二极尖部分处的第二极连接的第二极基座可以位于第一和第二极之间。此外，可以在第一导电线圈上方包括额外的导电线圈。

87. 发明授权

US06176981B1 Wafer bias ring controlling the plasma potential in a sustained self-sputtering reactor 有权
标题翻译：晶片偏置环控制持续自溅射反应器中的等离子体电位
公开(公告)号：US06176981B1
公开(公告)日：2001-01-23
申请号：US09193099
申请日：1998-11-16
申请人： Liubo Hong , John Forster , Jianming Fu
发明人： Liubo Hong , John Forster , Jianming Fu
IPC分类号： C23C1434
CPC分类号： H01J37/3438 , C23C14/14 , C23C14/3457 , H01J37/3405
摘要： A plasma reactor for physical vapor deposition (PVD), also known as sputtering, which is adapted so that the atomic species sputtered from the target can self-sustain the plasma without the need of a working gas such as argon. The method is particularly useful for sputtering copper. According to the invention, a bias ring arranged around the wafer and rising somewhat above it is positively electrically biased to control the plasma potential, and hence to control the energy and directionality of the ions being sputter deposited on the wafer. The bias ring may be a separate biasing element which can be positioned at a selected height above the wafer.
摘要翻译：用于物理气相沉积（PVD）的等离子体反应器，也称为溅射，其适于使得从目标溅射的原子物质能够自动维持等离子体而不需要诸如氩的工作气体。该方法对于溅射铜是特别有用的。根据本发明，布置在晶片周围并在其上方升高的偏置环被正向电偏压以控制等离子体电位，并且因此控制溅射沉积在晶片上的离子的能量和方向性。偏置环可以是可以位于晶片上方的选定高度处的单独的偏置元件。

88. 发明授权

US5897752A Wafer bias ring in a sustained self-sputtering reactor 失效
标题翻译：持续自溅射反应器中的晶圆偏置环
公开(公告)号：US5897752A
公开(公告)日：1999-04-27
申请号：US859300
申请日：1997-05-20
申请人： Liubo Hong , John Forster , Jianming Fu
发明人： Liubo Hong , John Forster , Jianming Fu
IPC分类号： H01L21/203 , C23C14/14 , C23C14/34 , H01J37/34 , H01L21/285
CPC分类号： H01J37/3438 , C23C14/14 , C23C14/3457 , H01J37/3405
摘要： A plasma reactor for physical vapor deposition (PVD), also known as sputtering, which is adapted so that the atomic species sputtered from the target can self-sustain the plasma without the need of a working gas such as argon. The method is particularly useful for sputtering copper. According to the invention, a bias ring arranged around the wafer and rising above it is electrically biased to control the plasma potential, and hence to control the energy and directionality of the ions being sputter deposited on the wafer. The bias ring can be either a separate biasing element which can be positioned at a selected height above the wafer or a clamping ring clamping the wafer to the pedestal but having a biasing surface electrically insulated from the wafer and the pedestal.
摘要翻译：用于物理气相沉积（PVD）的等离子体反应器，也称为溅射，其适于使得从目标溅射的原子物质能够自动维持等离子体而不需要诸如氩的工作气体。该方法对于溅射铜是特别有用的。根据本发明，布置在晶片周围并在其上方升高的偏置环被电偏压以控制等离子体电位，并且因此控制溅射沉积在晶片上的离子的能量和方向性。偏置环可以是可以位于晶片上方的选定高度处的单独的偏置元件或将晶片夹持到基座但具有与晶片和基座电绝缘的偏置表面的夹紧环。

89. 发明授权

US08969982B2 Bottom electrode for MRAM device 有权
标题翻译： MRAM器件底电极
公开(公告)号：US08969982B2
公开(公告)日：2015-03-03
申请号：US12927670
申请日：2010-11-19
申请人： Rongfu Xiao , Cheng T. Horng , Ru-Ying Tong , Chyu-Jinh Torng , Tom Zhong , Witold Kula , Terry Kin Ting Ko , Wei Cao , Wai-Ming J. Kan , Liubo Hong
发明人： Rongfu Xiao , Cheng T. Horng , Ru-Ying Tong , Chyu-Jinh Torng , Tom Zhong , Witold Kula , Terry Kin Ting Ko , Wei Cao , Wai-Ming J. Kan , Liubo Hong
IPC分类号： H01L29/82 , H01L43/12 , H01L43/08
CPC分类号： H01L43/12 , G11C11/161 , H01L43/08
摘要： A multi-layered bottom electrode for an MTJ device on a silicon nitride substrate is described. It comprises a bilayer of alpha tantalum on ruthenium which in turn lies on a nickel chrome layer over a second tantalum layer.
摘要翻译：描述了用于氮化硅衬底上的MTJ器件的多层底电极。它包括在钌上的α钽的双层，其又位于第二钽层上的镍铬层上。

90. 发明授权

US08553371B2 TMR reader without DLC capping structure 有权
标题翻译： TMR读卡器无DLC封盖结构
公开(公告)号：US08553371B2
公开(公告)日：2013-10-08
申请号：US12954508
申请日：2010-11-24
申请人： Honglin Zhu , Liubo Hong , Hicham M. Sougrati , Quang Le , Jui-Lung Li , Chando Park
发明人： Honglin Zhu , Liubo Hong , Hicham M. Sougrati , Quang Le , Jui-Lung Li , Chando Park
IPC分类号： G11B5/39
CPC分类号： G11B5/3163 , G01R33/098 , G11B5/3909 , G11B5/3929 , G11B5/3932
摘要： Embodiments herein generally relate to TMR readers and methods for their manufacture. The embodiments discussed herein disclose TMR readers that utilize a structure that avoids use of the DLC layer over the sensor structure and over the hard bias layer. The capping structure over the sensor structure functions as both a protective layer for the sensor structure and a CMP stop layer. The hard bias capping structure functions as both a protective structure for the hard bias layer and as a CMP stop layer. The capping structures that are free of DLC reduce the formation of notches in the second shield layer so that second shield layer is substantially flat.
摘要翻译：本文的实施方案通常涉及TMR读取器及其制造方法。本文讨论的实施例公开了TMR读取器，其利用了避免在传感器结构上以及硬偏置层上使用DLC层的结构。传感器结构上的封盖结构用作传感器结构的保护层和CMP停止层。硬偏置封盖结构既用作硬偏置层的保护结构又用作CMP停止层。没有DLC的封盖结构减少了第二屏蔽层中的凹口的形成，使得第二屏蔽层基本上是平的。

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