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81. 发明授权

US08300471B2 Non-volatile semiconductor memory having multiple external power supplies 有权
标题翻译：具有多个外部电源的非易失性半导体存储器
公开(公告)号：US08300471B2
公开(公告)日：2012-10-30
申请号：US13096874
申请日：2011-04-28
申请人： Jin-Ki Kim , Peter Gillingham
发明人： Jin-Ki Kim , Peter Gillingham
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
摘要翻译：存储器件包括诸如用于存储数据的闪存的核心存储器。存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。另外，存储器件包括用于接收第二电压的第二电源输入。存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。电源管理电路将内部电压提供或传送到闪存。由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

82. 发明授权

US08295115B2 Dynamic random access memory with fully independent partial array refresh function 有权
标题翻译：具有完全独立的部分阵列刷新功能的动态随机存取存储器
公开(公告)号：US08295115B2
公开(公告)日：2012-10-23
申请号：US13072097
申请日：2011-03-25
申请人： Jin-Ki Kim , HakJune Oh
发明人： Jin-Ki Kim , HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
摘要翻译：动态随机存取存储器件包括多个存储器子块。每个子块具有连接多个数据存储单元的多个字线。部分阵列自刷新（PASR）配置设置是独立制作的。根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。可以选择子块地址的任何种类的组合。因此，存储器子块被完全独立地刷新。用于数据保留的用户可选择的存储器阵列提供有效的存储器控制编程，特别是对于低功率移动应用。

83. 发明授权

US08289805B2 Non-volatile memory bank and page buffer therefor 有权
标题翻译：非易失性存储器和页缓冲器
公开(公告)号：US08289805B2
公开(公告)日：2012-10-16
申请号：US12879566
申请日：2010-09-10
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C8/00
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
摘要翻译：一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。记忆库分为两半，每半部分分为上下扇区。每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据通道内核减少了通常用于布线宽数据总线的芯片面积。因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

84. 发明授权

US08195839B2 Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection 失效
标题翻译：串行互连中无论混合设备类型如何，都可以生成标识符的设备和方法
公开(公告)号：US08195839B2
公开(公告)日：2012-06-05
申请号：US12892215
申请日：2010-09-28
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/109
摘要： A method and apparatus for assigning a device identifier for a plurality of devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) in a serial interconnection configuration are disclosed. One device of the serial interconnection configuration receives a device identifier (ID) and a device type (DT) as a packet through its serial input connection. A first determination is performed as to whether the DT of the device contains pre-defined data corresponding to one including all device types to provide a first determination result; and a second determination of the DT of the device is performed in response to the received DT to provide a second determination result. An ID is produced and output to a next device in response to the first and second determination results. The received ID or the produced ID is assigned to the respective devices.
摘要翻译：公开了一种在串行互连配置中为多个混合类型的设备（例如，DRAM，SRAM，MRAM，以及NAND，NOR和AND型闪存）分配设备标识符的方法和装置。串行互连配置的一个设备通过其串行输入连接接收设备标识符（ID）和设备类型（DT）作为数据包。执行关于设备的DT是否包含对应于包括所有设备类型的预定数据以提供第一确定结果的第一确定; 并且响应于接收的DT执行设备的DT的第二确定，以提供第二确定结果。响应于第一和第二确定结果产生ID并将其输出到下一个设备。所接收的ID或产生的ID被分配给各个设备。

85. 发明申请

US20120066442A1 SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的页面缓冲器操作的系统和方法
公开(公告)号：US20120066442A1
公开(公告)日：2012-03-15
申请号：US13302413
申请日：2011-11-22
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
摘要翻译：提供了系统和方法，用于使用通过公共总线连接到存储器控制器的存储器件的页缓冲器。使用存储器件的页缓冲器作为写入存储器件的存储器单元的数据的临时缓存。这可以允许内存控制器使用内存设备作为临时缓存，以便内存控制器可以释放自己内存中的空间。

86. 发明申请

US20120033497A1 NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE 有权
标题翻译：具有可配置页尺寸的非易失性存储器件
公开(公告)号：US20120033497A1
公开(公告)日：2012-02-09
申请号：US13276856
申请日：2011-10-19
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储器件中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

87. 发明申请

US20110314206A1 APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE 有权
标题翻译：使用存储器件的缓冲器作为临时缓存的装置和方法
公开(公告)号：US20110314206A1
公开(公告)日：2011-12-22
申请号：US13215789
申请日：2011-08-23
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G06F12/08
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.
摘要翻译：提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件中的空间。因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。

88. 发明授权

US08068365B2 Non-volatile memory device having configurable page size 有权
标题翻译：具有可配置页面大小的非易失性存储器件
公开(公告)号：US08068365B2
公开(公告)日：2011-11-29
申请号：US12329929
申请日：2008-12-08
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

89. 发明申请

US20110267896A1 Non-Volatile Semiconductor Memory with Page Erase 有权
标题翻译：非易失性半导体存储器，具有页擦除
公开(公告)号：US20110267896A1
公开(公告)日：2011-11-03
申请号：US13169231
申请日：2011-06-27
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C7/20 , G11C8/08 , G11C16/0483 , G11C16/14 , G11C16/344 , G11C16/3445
摘要： In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.
摘要翻译：在非易失性存储器中，少于一个完整的块可能会被擦除为一个或多个页面。通过通过晶体管将选择电压施加到多个选定字线中的每一个，并且通过传输晶体管将未选择的电压施加到所选块的多个未选择字线中的每一个。将衬底电压施加到所选块的衬底。可以将公共选择电压施加到每个所选择的字线，并且可以将公共未选择电压施加到每个未选择的字线。选择和取消选择电压可以应用于选择块的任何字线。页面擦除验证操作可以应用于具有多个擦除页面和多个非寻址页面的块。

90. 发明申请

US20110261616A1 WRITE SCHEME IN PHASE CHANGE MEMORY 审中-公开
标题翻译：相变记忆中的写入方案
公开(公告)号：US20110261616A1
公开(公告)日：2011-10-27
申请号：US13093923
申请日：2011-04-26
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/0061 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2013/0088 , G11C2213/72
摘要： A method for writing a phase change memory includes receiving an input data corresponding to a plurality of memory cells, while reading a previous data from the plurality of memory cells and comparing the input data with the previous data. Upon determining that the input data is different from the previous data for one or more of the plurality of memory cells, and upon determining that a current value of a write counter is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the current value of the writer counter is incremented.
摘要翻译：用于写入相变存储器的方法包括：从多个存储器单元读取先前数据并将输入数据与先前数据进行比较，接收与多个存储器单元相对应的输入数据。在确定输入数据与多个存储器单元中的一个或多个的先前数据不同时，并且在确定写计数器的当前值小于最大值时，多个存储器单元中的一个或多个用输入数据编程，写入计数器的当前值递增。

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