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71. 发明授权

US06202017B1 Circuit configuration for controlling electric or electromechanical consumers 失效
标题翻译：用于控制电力或机电消费者的电路配置
公开(公告)号：US06202017B1
公开(公告)日：2001-03-13
申请号：US07989027
申请日：1993-07-15
申请人： Hans Wilhelm Bleckmann , Heinz Loreck , Michael Zydek , Wolfgang Fey , Peter Jones
发明人： Hans Wilhelm Bleckmann , Heinz Loreck , Michael Zydek , Wolfgang Fey , Peter Jones
IPC分类号： G06F930
CPC分类号： B60T8/885 , B60T2270/408 , B60T2270/414
摘要： A circuit configuration for controlling a major number of consumers (5) such as the electromagnetically operable multi-directional valves of an anti-lock control system (MWV1-MWVn) comprises a control unit (2, 3) whose output signals can be fed to the consumers (5) via amplifier stages (4). The individual amplifier stages (4; VS1-VSn) are designed as so-called “intelligent power drivers” and essentially consist of a power amplifier (18) with integrated electronic controls and monitors. The control unit (2, 3) and the amplifier stages (4; VS1-VSn) are interconnected to form a closed loop or chain. Data transfer is performed from a synchronous serial interface of the control unit (2, 3), via the individual amplifier stages (4; VS1-VSn) and back to a serial entry of the control unit (2, 3).
摘要翻译：用于控制诸如反锁定控制系统（MWV1-MWVn）的电磁可操作多方向阀（5）的大量消耗器（5）的电路配置包括控制单元（2,3），其输出信号可被馈送到消费者（5）通过放大器级（4）。单个放大器级（4; VS1-VSn）被设计为所谓的“智能功率驱动器”，并且基本上由具有集成电子控制和监视器的功率放大器（18）组成。控制单元（2,3）和放大器级（4; VS1-VSn）互连以形成闭环或链。数据传输通过控制单元（2,3）的同步串行接口，经由各个放大器级（4; VS1-VSn）并返回到控制单元（2,3）的串行输入。

72. 再颁专利

USRE38679E1 Data processor and method of processing data 有权
标题翻译：数据处理器和数据处理方法
公开(公告)号：USRE38679E1
公开(公告)日：2004-12-28
申请号：US09848253
申请日：2001-05-04
申请人： Masahito Matsuo , Toyohiko Yoshida
发明人： Masahito Matsuo , Toyohiko Yoshida
IPC分类号： G06F930
CPC分类号： G06F9/3893 , G06F9/30014 , G06F9/30072 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30178 , G06F9/322 , G06F9/325 , G06F9/3552 , G06F9/3822 , G06F9/3853 , G06F9/3889
摘要： A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes two data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).

73. 发明授权

US06832307B2 Instruction fetch buffer stack fold decoder for generating foldable instruction status information 有权
标题翻译：指令提取缓冲栈折叠解码器，用于产生可折叠指令状态信息
公开(公告)号：US06832307B2
公开(公告)日：2004-12-14
申请号：US09909121
申请日：2001-07-19
申请人： Nicholas J. Richardson
发明人： Nicholas J. Richardson
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017
摘要： A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.
摘要翻译：多个折叠解码器各自耦合到指令获取缓冲器堆栈内的不同的连续条目集合，并检查可能被折叠的可变数量的可变长度指令的连续条目的内容。标识可折叠（如果有的话）中可能被折叠的每个指令的数目以及可折叠的每个指令的大小的各组条目中的每一个的折叠信息由折叠解码器产生并存储在折叠解码器的第一条目中设置，然后发送到主解码器，以在解码期间用于折叠指令。

74. 发明授权

US06820190B1 Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions 有权
标题翻译：将宏指令分解为微指令的方法和计算机系统，并迫使并行发出至少两个微指令
公开(公告)号：US06820190B1
公开(公告)日：2004-11-16
申请号：US09496844
申请日：2000-02-02
申请人： Patrick Knebel , Kevin David Safford
发明人： Patrick Knebel , Kevin David Safford
IPC分类号： G06F930
CPC分类号： G06F9/30174 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3865
摘要： The present invention is a method for processing instructions by decomposing a macroinstruction into at least two microinstructions, executing the microinstructions in parallel, and linking the microinstructions such that they appear as though they were executed as a single functional unit. The present invention operates by determining whether certain exceptions occur in either of the functional units, according to SSE rules for exceptions. If an exception does occur in any of the linked microinstructions, then the execution of each of those microinstructions is canceled. This avoids the necessity of a back-off or undo mechanism.
摘要翻译：本发明是一种通过将宏指令分解成至少两个微指令来并行执行微指令来处理指令的方法，并且连接微指令，使得它们看起来像单个功能单元一样被执行。根据例外的SSE规则，本发明通过确定在任一功能单元中是否发生某些异常来进行操作。如果在任何连接的微指令中发生异常，那么这些微指令中的每一个的执行将被取消。这避免了退出或撤销机制的必要性。

75. 发明授权

US06779107B1 Computer execution by opportunistic adaptation 有权
标题翻译：计算机执行机会主义适应
公开(公告)号：US06779107B1
公开(公告)日：2004-08-17
申请号：US09429377
申请日：1999-10-28
申请人： John S. Yates
发明人： John S. Yates
IPC分类号： G06F930
CPC分类号： G06F9/45558 , G06F9/45554 , G06F2009/45583
摘要： A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class. The mode switch persists for instructions consecutively executed on behalf of a program that was in execution immediately before the timer expiry, beyond any exception handlers invoked consequent to the timer expiry. As each classified instruction comes up for execution in the instruction pipeline circuitry, the instruction pipeline circuitry executes the instruction in a mode determined, at least in part, by the value of the corresponding flag.
摘要翻译：微处理器芯片和微处理器芯片执行的方法。指令流水线电路具有用于处理至少一些指令的第一和第二正确模式。多个标志各自对应于在指令流水线电路中发生的一类指令。作为计算机的基本执行周期的一部分，流水线控制电路与指令流水线电路配合，以维持标志的值以记录在第一模式中尝试执行的故障，相应的各个指令类别的两个模式指令，由定时器到期触发以切换标志的值，从而将指令流水线电路从处理模式之一切换到相应指令类的另一个。代表在定时器到期之前正在执行的程序连续执行的指令，除了在定时器到期之后调用的任何异常处理程序之外，模式切换仍然存在。随着每个分类指令出现在指令流水线电路中执行，指令流水线电路以至少部分地由相应标志的值确定的模式执行指令。

76. 发明授权

US06751724B1 Method and apparatus for instruction fetching 失效
标题翻译：指令取出方法和装置
公开(公告)号：US06751724B1
公开(公告)日：2004-06-15
申请号：US09552118
申请日：2000-04-19
申请人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
发明人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
IPC分类号： G06F930
CPC分类号： G06F9/3814 , G06F9/3802
摘要： Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.
摘要翻译：本发明的实施例涉及在数据处理系统中的指令取出。一个方面涉及一种数据处理器（202），用于执行指令并根据取出大小从存储器（208）获取指令。该数据处理器（202）包括用于接收指令的第一输入（212），解码指令的控制逻辑（402）以及耦合到第一输入（212）和控制逻辑（400）的指令流水线（400）。指令流水线（400）响应于第一信号（214）将获取大小设置为第一大小和第二大小中的一个。因此，数据处理器（202）允许基于所访问设备的特性来改变指令获取策略，以便实现改进的性能。

77. 发明授权

US06732256B2 Method and apparatus for object code compression and decompression for computer systems 有权
标题翻译：用于计算机系统的目标代码压缩和解压缩的方法和装置
公开(公告)号：US06732256B2
公开(公告)日：2004-05-04
申请号：US10462675
申请日：2003-06-17
申请人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
发明人： Jörg Henkel , Wayne Wolf , Haris Lekatsas
IPC分类号： G06F930
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/30185
摘要： A code compression method and apparatus for system-level power optimization that lessens the requirements imposed on main memory size. The apparatus utilizes a post-cache architecture that has a decompression engine that decompresses compressed object code instructions using dictionary look-up tables, branching instruction controllers and mathematical derivations based on bit toggling. The decompression engine extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.
摘要翻译：用于系统级功率优化的代码压缩方法和装置，其减轻对主存储器大小的要求。该装置使用具有解压缩引擎的缓存后架构，其使用字典查找表，分支指令控制器和基于位切换的数学推导解压缩压缩目标代码指令。解压缩引擎使用总线压缩技术从存储器或指令/数据高速缓存中提取压缩指令，以在压缩指令/数据穿过总线时节省功率。

78. 发明授权

US06697933B1 Method and apparatus for fast, speculative floating point register renaming 有权
标题翻译：用于快速，推测浮点寄存器重命名的方法和装置
公开(公告)号：US06697933B1
公开(公告)日：2004-02-24
申请号：US09539221
申请日：2000-03-30
申请人： Gregory Pribush , Ronny Ronen , Bishara Shomar
发明人： Gregory Pribush , Ronny Ronen , Bishara Shomar
IPC分类号： G06F930
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： According to one aspect of the invention, a method is provided in which a current instance of an instruction is received. The current instance of the instruction contains a reference to a logical floating point register. A first rename phase is performed to convert the current's instance reference to the logical floating point register into a reference to an absolute register. A second rename phase is performed in parallel with the first rename phase to convert the reference to the absolute register into a reference to a physical register, based upon results obtained from performing the first rename phase with respect to a previous instance of the instruction.
摘要翻译：根据本发明的一个方面，提供一种接收指令的当前实例的方法。指令的当前实例包含对逻辑浮点寄存器的引用。执行第一重命名阶段以将当前的实例引用转换为逻辑浮点寄存器，以引用到绝对寄存器。与第一重命名阶段并行地执行第二重命名阶段，以基于相对于先前的指令实例执行第一重命名阶段获得的结果，将对绝对寄存器的引用转换为对物理寄存器的引用。

79. 发明授权

US06658554B1 Electronic processor providing direct data transfer between linked data consuming instructions 有权
标题翻译：电子处理器在链接的数据消耗指令之间提供直接数据传输
公开(公告)号：US06658554B1
公开(公告)日：2003-12-02
申请号：US09418522
申请日：1999-10-14
申请人： Andreas I. Moshovos , Gurindar S. Sohi
发明人： Andreas I. Moshovos , Gurindar S. Sohi
IPC分类号： G06F930
CPC分类号： G06F9/3834 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/3842 , G06F9/3859
摘要： A data dependence prediction technique is used to establish linkage between two instructions using data so that accessing the data from memory may be bypassed. Instead, the data retrieved in the first data using instruction is temporarily stored in a local register to be used by the second data using instruction. Parallel processing techniques of squashing are used in the event that the prediction is erroneous.
摘要翻译：使用数据相关性预测技术来建立使用数据的两条指令之间的链接，从而可以绕过存储器中的数据。相反，使用指令在第一数据中检索的数据被临时存储在本地寄存器中，以由第二数据使用指令使用。在预测错误的情况下使用挤压的并行处理技术。

80. 发明授权

US06629233B1 Secondary reorder buffer microprocessor 有权
标题翻译：二次重排缓冲微处理器
公开(公告)号：US06629233B1
公开(公告)日：2003-09-30
申请号：US09506527
申请日：2000-02-17
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F930
CPC分类号： G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction's dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.
摘要翻译：公开了一种方法，处理器和数据处理系统，用于实现最大化指令发布，尽管存在需要多个重命名寄存器的复杂指令。该方法包括从第一重排序缓冲器分配第一重命名寄存器，用于存储受复合指令影响的第一寄存器的内容。然后分配来自第二重排序缓冲器的第二重命名寄存器用于存储受复合指令影响的第二寄存器的内容。在其中第一重排序缓冲器支持每个周期的最大分配数量的实施例中，使用第二重排序缓冲器分配第二寄存器防止复指令在第一重排序缓冲器中需要多个分配时隙。该方法还可以包括发出包含对在二次重排序缓冲器中分配的寄存器的依赖性的第二指令。在一个实施例中，指示第二指令对在二次重排序缓冲器中分配的寄存器的依赖性的重新排序缓冲器信息与第二指令相关联，使得当随后发出第二指令时，重排序缓冲器信息用于将发布单元限制为仅检查辅助重新排序缓冲区以获取依赖关系。

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