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71. 发明授权

US08619882B2 Data modulation circuit 有权
标题翻译：数据调制电路
公开(公告)号：US08619882B2
公开(公告)日：2013-12-31
申请号：US12330279
申请日：2008-12-08
申请人： Uichi Sekimoto
发明人： Uichi Sekimoto
IPC分类号： H04B14/06
CPC分类号： H03M7/3026 , H03M7/3031
摘要： A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.
摘要翻译：数据调制电路具有添加输入信号的加法器和存储器件的输出信号; 以及输出电路部分，将加法器的输出信号鉴别和量化预定阈值。存储器件接收并保持加法器的输出信号和预定信号，并将保持的信号作为存储器件的输出信号提供给加法器。

72. 发明申请

US20130064324A1 Digital Modulation With Arbitrary Input Sampling and Output Modulation Frequencies 有权
标题翻译：数字调制与任意输入采样和输出调制频率
公开(公告)号：US20130064324A1
公开(公告)日：2013-03-14
申请号：US13484485
申请日：2012-05-31
申请人： Bernard Ginetti , Zhongxuan Zhang
发明人： Bernard Ginetti , Zhongxuan Zhang
IPC分类号： H04B15/00 , H04L27/12
CPC分类号： H03M3/41 , H03C3/00 , H03M7/3017 , H03M7/3026 , H03M7/304 , H04L27/04
摘要： An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.
摘要翻译：选择调制信号的任意调制频率。调制信号被应用于信息承载信号，其中通过数字信号处理操作进行这种调制。数字调制信号是分辨率降低的，并且由此引入的量化噪声被形成为在调制频率下在分辨率降低调制器的噪声传递函数中定位频谱零点。因此，可以独立于将分辨率降低的采样转换为模拟信号的时钟频率来选择调制频率。

73. 发明申请

US20110140942A1 Conversion of a Discrete Time Quantized Signal into a Continuous Time, Continuously Variable Signal 有权
标题翻译：将离散时间量化信号转换为连续时间，连续可变信号
公开(公告)号：US20110140942A1
公开(公告)日：2011-06-16
申请号：US12970379
申请日：2010-12-16
申请人： Christopher Pagnanelli
发明人： Christopher Pagnanelli
IPC分类号： H03M1/66
CPC分类号： H03M3/50 , H03M3/358 , H03M3/502 , H03M7/3026 , H03M7/3033
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive non-linear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
摘要翻译：尤其提供了用于将离散时间量化信号转换成连续时间连续可变信号的系统，装置，方法和技术。示例性转换器优选地包括：（1）多个过采样转换器，每个处理不同的频带，并行操作; （2）多速率（即多相）Δ-Σ调制器（优选二阶或更高）; （3）多位量化器; （4）多位到可变电平信号转换器，如电阻梯形网络或电流源网络; （5）自适应非线性比特映射以补偿多比特到可变等级信号转换器中的不匹配（例如，通过模拟这种不匹配，然后将所得到的噪声移动到将被滤波的频繁范围）通过相应的带通（重建）滤波器）; （6）多频带（例如可编程噪声传递函数响应）带通Δ-Σ调制器; 和/或（7）用于消除由模拟信号带通（重构）滤波器组引入的噪声和失真的数字预失真线性化器（DPL）。

74. 发明授权

US07720160B1 Phase noise shaping using sigma delta modulation in a timing recovery unit 有权
标题翻译：在定时恢复单元中使用Σ-Δ调制的相位噪声整形
公开(公告)号：US07720160B1
公开(公告)日：2010-05-18
申请号：US11639656
申请日：2006-12-14
申请人： James L. Gorecki , Tong Liu
发明人： James L. Gorecki , Tong Liu
IPC分类号： H04B14/06 , H04L7/00 , H03M1/20
CPC分类号： H04B14/062 , H03L7/0812 , H03L7/093 , H03M3/50 , H03M7/3026 , H04L7/0025 , H04L7/033
摘要： A method and apparatus for converting a high precision digital word into a high precision analog signal is disclosed. A sigma delta modulator applies a digital input signal to a dither signal to generate a combined signal for sampling. A digital-to-analog converter quantizes the combined signal. An analog filter provides a cutoff at a bandwidth of interest to remove out of band quantization noise and signals. An I transfer function and a Q transfer function can be coupled between the sigma delta modulator and the digital-to-analog converter for mapping of the combined signal. The apparatus can also include a phase interpolator for receiving the output signal and outputting a clock recovery phase.
摘要翻译：公开了一种用于将高精度数字字转换成高精度模拟信号的方法和装置。 Σ-Δ调制器将数字输入信号施加到抖动信号以产生用于采样的组合信号。数模转换器对组合信号进行量化。模拟滤波器在感兴趣的带宽上提供截止以去除带外量化噪声和信号。可以在Σ-Δ调制器和数 - 模转换器之间耦合I传递函数和Q传递函数，用于映射组合信号。该装置还可以包括用于接收输出信号并输出时钟恢复阶段的相位插值器。

75. 发明申请

US20100117730A1 D/A converter circuit and digital input class-D amplifier 有权
标题翻译： D / A转换器电路和数字输入D类放大器
公开(公告)号：US20100117730A1
公开(公告)日：2010-05-13
申请号：US12583792
申请日：2009-08-26
申请人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
发明人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
IPC分类号： H03F3/217 , H03M1/66
CPC分类号： H03F3/2173 , H03M1/0639 , H03M1/0673 , H03M1/822 , H03M3/328 , H03M3/50 , H03M3/506 , H03M7/3026
摘要： The present invention provides a D/A converter circuit which enables D/A conversion with a high precision and can prevent occurrence of a limit cycle component in the case where an input signal is low, and can also prevent the effect of dither signal from occurring in an analog signal which is a D/A conversion result.A dither signal generation section 505 outputs a dither signal (DITHER) which is an alternating current signal and a reversal dither signal (DITHER_N) inverted from the dither signal. A DEM decoder 502 processes an input digital signal including a component of the dither signal (DITHER), and outputs a plurality of lines of time-series digital signals having a density of “1” or “0” conforming to the input digital signal to be processed. An analog addition section 503 converts a plurality of lines of time-series digital signals and the reversal dither signal (DITHER_N) into an analog signal respectively and adds them, and outputs an analog signal which is a D/A conversion result.
摘要翻译：本发明提供了一种D / A转换器电路，其能够以高精度实现D / A转换，并且可以防止在输入信号低的情况下出现极限循环分量，并且还可以防止抖动信号的影响在作为D / A转换结果的模拟信号中。抖动信号生成单元505输出作为交流信号的抖动信号（DITHER）和从抖动信号反转的反转抖动信号（DITHER_N）。 DEM解码器502处理包括抖动信号（DITHER）分量的输入数字信号，并输出符合输入数字信号的密度为“1”或“0”的多行时间序列数字信号到被处理。模拟加法部分503将多行时间序列数字信号和反相抖动信号（DITHER_N）分别转换为模拟信号并将其相加，并输出作为D / A转换结果的模拟信号。

76. 发明授权

US07710300B2 Segmented data shuffler apparatus for a digital to analog converter (DAC) 有权
标题翻译：用于数模转换器（DAC）的分段数据洗牌装置
公开(公告)号：US07710300B2
公开(公告)日：2010-05-04
申请号：US12081547
申请日：2008-04-17
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M3/00 , H03M1/66
CPC分类号： H03M3/416 , H03M3/50 , H03M7/3026
摘要： A sigma-delta digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation, including a primary and a secondary sigma-delta modulator. The primary sigma-delta modulator produces a primary digital segment and a primary quantization error. A primary sample is delayed, decoded, scrambled and converted to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment which is noise shaped by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment which is decoded, scrambled, converted and scaled to produce a secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.
摘要翻译： Σ-Δ数模转换器（DAC）模块通过包括初级和次级Σ-Δ调制器的分段将数字输入信号转换成模拟输出信号。初级Σ-Δ调制器产生主数字段和主量化误差。主要样本被延迟，解码，加扰和转换以产生主要的模拟段。次级Σ-Δ调制主量化误差以产生次级数字段，其由主要Σ-Δ调制器的噪声传递函数进行噪声整形，以产生噪声形状的次级数字段，其被解码，加扰，转换和缩放为产生二次模拟段。一个加法器结合了主要的模拟段和二级模拟段，以产生模拟输出信号。

77. 发明申请

US20090251346A1 Segmented data shuffler apparatus for a digital to analog converter (DAC) 有权
标题翻译：用于数模转换器（DAC）的分段数据洗牌装置
公开(公告)号：US20090251346A1
公开(公告)日：2009-10-08
申请号：US12081547
申请日：2008-04-17
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M3/416 , H03M3/50 , H03M7/3026
摘要： A method and apparatus is disclosed to convert a digital input signal to an analog output signal. A digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation. A primary sigma-delta modulator sigma-delta modulates the digital input signal to produce a primary digital segment and a primary quantization error. A primary sample delay delays the primary digital segment to produce a delayed primary digital segment. A primary decoder module decodes the delayed primary digital segment to produce a primary decoded digital signal. A primary scrambler scrambles the primary decoded digital signal to produce a primary scrambled digital signal. A primary DAC converts the primary scrambled digital signal from a digital representation to an analog representation to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment. A secondary noise module shapes the secondary digital segment by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment. A secondary decoder module decodes the noise shaped secondary digital segment to produce a secondary decoded digital signal. A secondary scrambler scrambles the secondary decoded digital signal to produce a secondary scrambled digital signal. A secondary DAC converts the secondary scrambled digital signal from a digital representation to an analog representation to produce a secondary analog segment. A scaling module scales the magnitude of the secondary analog segment by a scaling factor to produce the secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.
摘要翻译：公开了一种将数字输入信号转换为模拟输出信号的方法和装置。数模转换器（DAC）模块通过分段将数字输入信号转换为模拟输出信号。初级Σ-Δ调制器Σ-Δ调制数字输入信号以产生主数字段和一次量化误差。主采样延迟延迟主要数字段以产生延迟的主要数字段。主解码器模块解码延迟的主要数字段以产生主要解码的数字信号。主扰频器对主解码数字信号进行加扰，以产生主加扰数字信号。主DAC将主加扰数字信号从数字表示转换为模拟表示以产生主要模拟段。次级Σ-Δ调制主量化误差以产生次级数字段。辅助噪声模块通过主要Σ-Δ调制器的噪声传递函数来形成次级数字段，以产生噪声形状的次级数字段。次级解码器模块对噪声形状的次级数字段进行解码以产生二次解码的数字信号。次扰频器对二次解码的数字信号进行加扰，以产生二次加扰的数字信号。次级DAC将辅助加扰数字信号从数字表示转换为模拟表示以产生次级模拟段。缩放模块将次级模拟段的幅度缩放比例因子以产生次级模拟段。一个加法器结合了主要的模拟段和二级模拟段，以产生模拟输出信号。

78. 发明申请

US20090040086A1 DWA STRUCTURE AND METHOD THEREOF, DIGITAL-TO-ANALOG SIGNAL CONVERSION METHOD AND SIGNAL ROUTING METHOD 失效
标题翻译： DWA结构及其方法，数字到模拟信号转换方法和信号路由方法
公开(公告)号：US20090040086A1
公开(公告)日：2009-02-12
申请号：US11835094
申请日：2007-08-07
申请人： Ghia-Ming Hong , Chia-Wei Chang , Yan-Hua Peng , Kuang-Chih Liu , Chung-Fu Lin
发明人： Ghia-Ming Hong , Chia-Wei Chang , Yan-Hua Peng , Kuang-Chih Liu , Chung-Fu Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0665 , H03M1/804 , H03M3/502 , H03M7/165 , H03M7/3026
摘要： A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.
摘要翻译：提供了包括第一延迟单元，二进制到温度计代码转换器，加法器，第二延迟单元，解码器，桶形移位器和多个信号线的数据加权平均（DWA）结构。第一延迟单元延迟输入数字信号。二进制到温度计代码转换器将第一延迟单元的输出信号转换成热代码。第二延迟单元延迟加法器的输出信号。加法器将输入数字信号加到第二延迟单元的输出信号上。解码器解码第二延迟单元的输出信号。桶形移位器根据解码器的输出信号从热代码生成输出信号。信号线将桶形移位器的输出信号路由到两个独立的控制信号组。

79. 发明授权

US07388438B2 ΣΔ modulator for PLL circuit 有权
标题翻译：用于PLL电路的SigmaDelta调制器
公开(公告)号：US07388438B2
公开(公告)日：2008-06-17
申请号：US11042136
申请日：2005-01-26
申请人： Morihito Hasegawa
发明人： Morihito Hasegawa
IPC分类号： H03L7/18 , H03M3/00
CPC分类号： H03M7/3006 , H03L7/1976 , H03M7/3026 , H03M7/304
摘要： A ΣΔ modulator for producing a modulation signal for modulating a frequency division ratio of a comparison frequency divider of a PLL circuit. A plurality of integrators connected in series integrate an input signal and output overflow signals when the integrated value has exceeded a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies predetermined coefficients by output signals output from the differentiators and adds the multiplied values. The absolute values of the predetermined coefficients of the adder are set to be less than the predetermined value. This setting decreases the modulation width of the modulation signal.
摘要翻译： SigmaDelta调制器，用于产生用于调制PLL电路的比较分频器的分频比的调制信号。当积分值超过预定值时，串联连接的多个积分器集成输入信号和输出溢出信号。微分器传输积分器的溢出信号。加法器通过从微分器输出的输出信号乘以预定系数，并将相乘的值相加。加法器的预定系数的绝对值被设定为小于预定值。该设置降低调制信号的调制宽度。

80. 发明授权

US07378997B2 Method of reducing inter-symbol interference, a sigma-delta converter for performing this method and a storage medium conveying information generated by this method 有权
标题翻译：降低符号间干扰的方法，用于执行该方法的Σ-Δ转换器和传送由该方法产生的信息的存储介质
公开(公告)号：US07378997B2
公开(公告)日：2008-05-27
申请号：US10594488
申请日：2005-03-23
申请人： Bas Maria Putter
发明人： Bas Maria Putter
IPC分类号： H03M1/06
CPC分类号： H03M3/322 , H03M1/0668 , H03M3/424 , H03M3/43 , H03M3/464 , H03M7/3006 , H03M7/3026 , H03M7/3028
摘要： A method and arrangement of reducing inter-symbol interference occurring at the digital to analog conversion of a one bit digital signal is provided. During the generation of the one-bit digital signal in a sigma-delta converter the edge-density of the digital signal is measured, the result of the measurement is multiplied with the digital signal and the result of the multiplication is added to the input of the quantizer generating the digital signal. The invention also covers storage media comprising a one-bit digital signal generated in accordance with the invention.
摘要翻译：提供了减少在一位数字信号的数模转换时发生的符号间干扰的方法和装置。在Σ-Δ转换器中产生1位数字信号期间，测量数字信号的边缘密度，测量结果与数字信号相乘，乘法运算结果加到量化器产生数字信号。本发明还涉及包括根据本发明生成的一比特数字信号的存储介质。

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