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71. 发明申请

WO2017112210A1 SINGLE AMPLIFER BI-QUAD SIGMA-DELTA MODULATOR 审中-公开
标题翻译：单放大器双四线SIGMA-DELTA调制器
公开(公告)号：WO2017112210A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063073
申请日：2016-11-21
申请人： INTEL IP CORPORATION
发明人： KAUFFMAN, John G. , SCHUETZ, Udo
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/30 , H03M3/386 , H03M3/448 , H03M3/452 , H03M3/454
摘要： Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier.
摘要翻译：一些实施例包括使用包括积分器的第一级，耦合到第一级的第二级，包括放大器，第一电容器和与第一级串联耦合的第二电容器的第二级的装置和方法，放大器的输入节点和输出节点之间的第一电容器，耦合到放大器的输出节点的量化器以及耦合到量化器的输出节点和第一和第二级的反馈路径，反馈路径包括数模转换器（DAC），DAC包括耦合到量化器的输出节点的输入节点和耦合到放大器的输入节点的输出节点。

72. 发明申请

WO2012119922A1 METHOD FOR USING A SENSOR SYSTEM HAVING A SINGLE-BIT QUANTIZER AND A MULTI-BIT FEEDBACK LOOP 审中-公开
标题翻译：使用具有单位量测器和多位反馈环路的传感器系统的方法
公开(公告)号：WO2012119922A1
公开(公告)日：2012-09-13
申请号：PCT/EP2012/053552
申请日：2012-03-01
申请人： PGS GEOPHYSICAL AS , HAASL, Sjoerd , HEDENSTIERNA, Nils , ANDERSSON, Gert , WESTBERG, David , CARLSSON, Mats
发明人： HAASL, Sjoerd , HEDENSTIERNA, Nils , ANDERSSON, Gert , WESTBERG, David , CARLSSON, Mats
IPC分类号： H03M3/02
CPC分类号： H03M3/434 , H03M3/452 , H03M3/454
摘要： A modulator (100) is provided in operative engagement with a sensor element (102) having a plurality of electrodes. The modulator (100) has a single-bit quantizer (110) electrically connected to a digital accumulator (107). The accumulator (107) accumulates output information received from the single-bit quantizer (110). The accumulator (107) converts the accumulated output information received from the single-bit quantizer (110) to a multi-bit feedback signal (108) and sends the multi-bit feedback signal (109) in a primary feedback loop (108) back to the sensor element (102). The quantizer (110) sends a single-bit feedback signal (111) in a secondary feedback loop (112) back to a point before the quantizer (110).
摘要翻译：调制器（100）设置成与具有多个电极的传感器元件（102）可操作地接合。调制器（100）具有电连接到数字累加器（107）的单比特量化器（110）。累加器（107）累积从单位量化器（110）接收的输出信息。累加器（107）将从单位量化器（110）接收的累积输出信息转换为多位反馈信号（108），并将多位反馈信号（109）发送回主回馈环路（108）到传感器元件（102）。量化器（110）将次级反馈回路（112）中的单位反馈信号（111）发送回量化器（110）之前的点。

73. 发明申请

WO2012035674A1 デルタシグマ変調器审中-公开
标题翻译： DELTA-SIGMA调制器
公开(公告)号：WO2012035674A1
公开(公告)日：2012-03-22
申请号：PCT/JP2011/000347
申请日：2011-01-24
申请人：パナソニック株式会社 , 匂坂雅彦 , 足立寿史
发明人：匂坂　雅彦 , 足立　寿史
IPC分类号： H03M3/02
CPC分类号： H03M3/362 , H03M3/366 , H03M3/452
摘要：　本発明のデルタシグマ変調器は、複数段の積分器（４１～４５）のうち、少なくとも１つの積分器（４１，４２）がオープンループゲインが可変である可変利得差動増幅器（４６，４７）で構成されるとともに、残りの積分器（４３～４５）がオープンループゲインが固定である固定利得差動増幅器（４８～５０）で構成されており、発振しているか否かを判定し、発振していることを判定したときには可変利得差動増幅器（４６，４７）のオープンループゲインを減少させるように制御するオープンループゲイン制御手段（６２，６３）を備える。
摘要翻译：在该Δ-Σ调制器中，多个积分器（41至45）中的一个或多个（41,42）使用具有可变开环增益的可变增益差分放大器（46,47），并且剩余积分器（43至45 ）使用具有固定开环增益的固定增益差分放大器（48至50）。该Δ-Σ调制器设置有确定是否发生谐振的开环增益控制装置（62和63），并且如果确定发生谐振，则控制可变增益差分放大器（46）和47），以便降低其开环增益。

74. 发明申请

WO2010145836A1 INTEGRATOR 审中-公开
公开(公告)号：WO2010145836A1
公开(公告)日：2010-12-23
申请号：PCT/EP2010/003692
申请日：2010-06-18
申请人： ST-ERICSSON SA , PUTTER, Bas
发明人： PUTTER, Bas
IPC分类号： G05B11/40 , H03K7/06 , H03L7/24
CPC分类号： H03L7/24 , G06G7/18 , H03K7/06 , H03M3/43 , H03M3/448 , H03M3/452
摘要： An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to oscillate at an oscillation frequency higher than the frequencies of interest in the input signal. The loop includes a filter (160) for attenuating the oscillation signal to ensure that the amplification and phase shifting element (170) can provide amplification for the input signal. The input signal is integrated and the integrated signal perturbs the zero crossings of the oscillation signal.
摘要翻译：积分器（100）包括具有形成回路并包括电容元件（140）的反馈路径（130）的放大和相移元件（170）。将输入信号相加到该环路中，并且该环路被布置成以比输入信号中感兴趣的频率高的振荡频率振荡。该环路包括用于衰减振荡信号的滤波器（160），以确保放大和移相元件（170）能够为输入信号提供放大。输入信号被积分，积分信号扰乱振荡信号的过零点。

75. 发明申请

WO2008094795A3 SYSTEMS AND METHODS FOR KICKBACK REDUCTION IN AN ADC 审中-公开
标题翻译：在ADC中减少KICKBACK的系统和方法
公开(公告)号：WO2008094795A3
公开(公告)日：2009-01-22
申请号：PCT/US2008051753
申请日：2008-01-23
申请人： TEXAS INSTRUMENTS INC , KOE WERN MING , PARK YONG-IN
发明人： KOE WERN MING , PARK YONG-IN
IPC分类号： H03M3/00 , H03M1/12
CPC分类号： H03M3/376 , H03M3/45 , H03M3/452
摘要： Various systems and methods for analog-to-digital conversion are disclosed. For example, some embodiments of the invention provide analog-to-digital conversion systems (400). The analog-to-digital conversion systems include a first integrator (410) and a second integrator (420), and a first summation element (450) and a second summation element (465). An output of the first summation element is electrically coupled to the first integrator, and an output of the first integrator is electrically coupled to the second integrator. An output of the second integrator is electrically coupled to the second summation element. The analog-to-digital conversion systems further include an analog-to-digital converter (440) that is electrically coupled to the first summation element via a digital-to-analog converter (430). An input (441) to the analog-to-digital conversion system is electrically coupled to the first summation element, and the input is electrically coupled to the second summation element via a kickback filter (401).
摘要翻译：公开了用于模数转换的各种系统和方法。例如，本发明的一些实施例提供模拟 - 数字转换系统（400）。模数转换系统包括第一积分器（410）和第二积分器（420），以及第一求和元件（450）和第二求和元件（465）。第一求和元件的输出电耦合到第一积分器，并且第一积分器的输出电耦合到第二积分器。第二积分器的输出电耦合到第二求和元件。模数转换系统还包括经由数模转换器（430）电耦合到第一求和元件的模拟 - 数字转换器（440）。模数转换系统的输入（441）电耦合到第一求和元件，并且该输入经由反冲滤波器（401）电耦合到第二求和元件。

76. 发明申请

WO2008076519A2 METHODS AND APPARATUS FOR A MULTI-MODE ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：用于多模式模数转换器的方法和装置
公开(公告)号：WO2008076519A2
公开(公告)日：2008-06-26
申请号：PCT/US2007082585
申请日：2007-10-26
申请人： FREESCALE SEMICONDUCTOR INC , ZHIXU ZHOU , ASCHIERI JULIAN , MIAILLE GERALD P
发明人： ZHIXU ZHOU , ASCHIERI JULIAN , MIAILLE GERALD P
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/43 , H03M3/452
摘要： A multi-mode analog-to-digital converter (100) includes a delta-sigma analog-to- digital converter circuit configured to receive the analog input (102) and produce a digital bit- stream (140) associated therewith, the delta-sigma analog-to-digital converter including at least one integrator configured to reset to an initial state in response to a reset signal. A digital filter circuit is configured to receive the digital bit-stream and produce two filtered outputs derived from the digital bit-stream. During one mode (e.g., a DC mode) the delta-sigma analog-to-digital converter circuit is configured to receive the reset signal and produce the digital bit-stream for a predetermined number of clock cycles, and the digital output corresponds to the first filtered output. In another mode (e.g., an AC mode), the delta-sigma analog-to-digital converter is configured to continuously produce the bit-stream, and the digital output corresponds to the second filtered output.
摘要翻译：多模式模数转换器（100）包括被配置为接收模拟输入（102）并产生与其相关联的数字位流（140）的Δ-Σ模数转换器电路，西格玛模数转换器，包括至少一个积分器，其被配置为响应于复位信号复位到初始状态。数字滤波器电路被配置为接收数字比特流并且产生从数字比特流导出的两个滤波的输出。在一种模式（例如，DC模式）期间，Δ-Σ模数转换器电路被配置为接收复位信号并产生预定数量的时钟周期的数字位流，并且数字输出对应于首先滤波输出。在另一模式（例如，AC模式）中，Δ-Σ模数转换器被配置为连续产生比特流，并且数字输出对应于第二滤波输出。

77. 发明申请

WO2008028142A3 INPUT TRACKING HIGH-LEVEL MULTIBIT QUANTIZER FOR DELTA-SIGMA ADC 审中-公开
标题翻译：用于DELTA-SIGMA ADC的输入跟踪高级多位量化器
公开(公告)号：WO2008028142A3
公开(公告)日：2008-05-02
申请号：PCT/US2007077412
申请日：2007-08-31
申请人： TEXAS INSTRUMENTS INC , YANG YUQING
发明人： YANG YUQING
IPC分类号： H03M1/66
CPC分类号： H03M1/146 , H03M1/361 , H03M1/365 , H03M3/424 , H03M3/452
摘要： A quantization circuit includes a plurality of resistors (R-0 to R-15), a plurality of tap points (16-3 to 16-15), and a plurality of coarse comparators (21-3 to 21-15). Each coarse comparator has a first input coupled to an input voltage (V Qin ) and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a "1 " only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators (24-1 to 24-3) each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a "1".
摘要翻译：量化电路包括多个电阻器（R-0至R-15），多个抽头点（16-3至16-15）以及多个粗略比较器（21-3至21-15）。每个粗略比较器具有耦合到输入电压（V IN）的第一输入和耦合到对应的粗略抽头点电压的第二输入。每个粗略比较器在第一阶段工作，只有当输入电压超过相应的粗抽头电压时才产生“1”。多个精细比较器（24-1至24-3）各自具有耦合到输入电压的第一输入，并且每个精细比较器在第二阶段期间操作以产生指示输入电压是否超过对应抽头的精细输出电平位于连接到最高粗比较器的抽头点正下方的一组抽头点的点电压产生“1”。

78. 发明申请

WO2006043207A1 SIGNAL RECEIVER AND MOBILE COMMUNICATION DEVICE 审中-公开
标题翻译：信号接收机和移动通信设备
公开(公告)号：WO2006043207A1
公开(公告)日：2006-04-27
申请号：PCT/IB2005/053344
申请日：2005-10-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN VELDHOVEN, Robert, Henrikus, Margaretha , BREEMS, Lucien, Johannes
发明人： VAN VELDHOVEN, Robert, Henrikus, Margaretha , BREEMS, Lucien, Johannes
IPC分类号： H03M3/04
CPC分类号： H03M3/394 , H03M3/424 , H03M3/452 , H03M3/462
摘要： A signal receiver processing circuit is for isolating a desired signal from analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) and an analog to digital converter (14) for providing a digital signal to a digital signal processor (15), the digital signal processor including a digital filter. The device has a control unit (16) for adjusting a filtering accuracy of the analog to digital converter (14) and/or the digital signal processor unit (15) in dependence of a signal quality of the input signal.
摘要翻译：信号接收机处理电路用于将期望的信号与容易受信号功率变化影响的模拟输入信号进行隔离。从无线电前端（12）。该装置具有可变增益放大器（13）和用于向数字信号处理器（15）提供数字信号的模数转换器（14），数字信号处理器包括数字滤波器。该装置具有控制单元（16），用于根据输入信号的信号质量来调节模数转换器（14）和/或数字信号处理器单元（15）的滤波精度。

79. 发明申请

WO2005011122A2 INTEGRATOR RESET MECHANISM 审中-公开
标题翻译：积分器重置机制
公开(公告)号：WO2005011122A2
公开(公告)日：2005-02-03
申请号：PCT/US2004021524
申请日：2004-07-01
申请人： ZARLINK SEMICONDUCTOR AB , DELIGHT GUY , LEREVEREND REMI
发明人： DELIGHT GUY , LEREVEREND REMI
IPC分类号： G06G7/186 , H03M1/06 , H03M3/00 , H03M3/02 , H03M1/00
CPC分类号： G06G7/1865 , H03M3/364 , H03M3/43 , H03M3/452
摘要： An integrator with a reset mechanism comprises an integration capacitor and a replacement integration capacitor, wherein the integration capacitor is replaced with the replacement integration capacitor during a reset operation. A method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method may further comprise temporarily removing the integration capacitor and replacing it with a reset capacitor multiple times during a single reset operation of the integrator.
摘要翻译：具有复位机构的积分器包括积分电容器和替换积分电容器，其中积分电容器在复位操作期间被替换积分电容器替换。一种重置积分器的方法包括在积分器的重置操作期间临时移除积分电容器并用重置电容器替换积分电容器。该方法还可以包括在积分器的单次复位操作期间临时移除积分电容器并用复位电容器多次替换它。

80. 发明申请

WO2014022410A1 LOW DISTORTION FEED-FORWARD DELTA-SIGMA MODULATOR 审中-公开
标题翻译：低失真进给前置三角形调制器
公开(公告)号：WO2014022410A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/052748
申请日：2013-07-30
申请人： QUALCOMM INCORPORATED
发明人： RAJAEE, Omid , DAI, Liang
IPC分类号： H03M3/00
CPC分类号： H03M3/452
摘要： A low distortion feed forward delta sigma modulator includes a first adder operable to receive a feedback signal and an input signal. The modulator also includes a first integrator operable to receive an output from the first adder, and a second integrator operable to receive an output from the first integrator. The modulator further includes a second adder operable to receive a second integrated path from the second integrator, a first integrating path from the first integrator and a first summing path from the input signal. The modulator also has a last integrator operable to receive an output from the second adder.
摘要翻译：低失真前馈ΔΣ调制器包括可操作以接收反馈信号和输入信号的第一加法器。调制器还包括可操作以接收来自第一加法器的输出的第一积分器和可操作以接收来自第一积分器的输出的第二积分器。调制器还包括第二加法器，可操作以从第二积分器接收第二集成路径，来自第一积分器的第一积分路径和来自输入信号的第一求和路径。调制器还具有可操作以接收来自第二加法器的输出的最后一个积分器。

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