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71. 发明授权

US06333237B1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06333237B1
公开(公告)日：2001-12-25
申请号：US09531690
申请日：2000-03-20
申请人： Hiroshi Yoshida
发明人： Hiroshi Yoshida
IPC分类号： H01L218228
CPC分类号： H01L21/8228
摘要： A method for manufacturing a semiconductor device separately forms two collector regions, two base extension regions, two base regions, and two collector extension regions on a first bipolar transistor forming region and a second bipolar transistor forming region that are formed on a semiconductor substrate, and includes a step of forming an emitter region on the first bipolar transistor region and forming, in the same process step, a base contact layer for an emitter electrode in the second bipolar transistor region as well, after which an emitter electrode is formed on the base contact layer.
摘要翻译：一种制造半导体器件的方法在半导体衬底上形成的第一双极晶体管形成区域和第二双极晶体管形成区域上分别形成两个集电极区域，两个基极延伸区域，两个基极区域和两个集电极延伸区域，以及包括在第一双极晶体管区域上形成发射极区域的步骤，并且在相同的工艺步骤中，在第二双极晶体管区域中形成用于发射极的基极接触层，之后在基底上形成发射电极接触层。

72. 发明授权

US06222249B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06222249B1
公开(公告)日：2001-04-24
申请号：US09339700
申请日：1999-06-24
申请人： Peter H Osborne , Martin C. Wilson
发明人： Peter H Osborne , Martin C. Wilson
IPC分类号： H01L27082
CPC分类号： H01L27/0826 , H01L21/8228
摘要： A number of npn and pnp bipolar transistors is formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others. The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidizing the silicon surface, and subsequently removing the oxide to leave the recess.
摘要翻译：多个npn和pnp双极晶体管形成在单芯片硅中，使得一些晶体管具有比其它晶体管更大的频率响应。通过将晶体管的集电极或发射极定位在芯片表面的凹陷部分中，较高频率的晶体管的发射极位于更靠近集电极的位置。通过局部氧化硅表面，以精确和可控的方式形成凹部，随后除去氧化物以离开凹槽。

73. 发明授权

US6146957A Method of manufacturing a semiconductor device having a buried region with higher impurity concentration 失效
标题翻译：具有杂质浓度较高的埋藏区域的半导体装置的制造方法
公开(公告)号：US6146957A
公开(公告)日：2000-11-14
申请号：US52082
申请日：1998-03-31
申请人： Youichi Yamasaki
发明人： Youichi Yamasaki
IPC分类号： H01L27/14 , H01L21/8222 , H01L21/8228 , H01L27/06 , H01L27/146 , H01L31/10 , H01L31/103
CPC分类号： H01L31/103 , H01L21/8228 , H01L27/0664 , H01L27/14609 , H01L27/14643
摘要： Since the PN junction of a photodiode is formed of a silicon substrate having a low impurity concentration and an epitaxial layer, the width of the depletion layer in the PN junction is formed wider, the parasitic capacitance by the junction capacitance is lowered, and the diffusion length of the silicon substrate is formed longer. Besides, a buried layer containing a high impurity concentration is formed by a high energy ion implantation method in such a depth that the buried layer cannot be depleted by a reverse voltage applied to the PN junction, which is served as a region to lead out the anode, which accordingly results in a low parasitic resistance at the anode. Thereby, the invention provides a semiconductor device including a photodetector and a method of manufacturing the same that achieves a high photoelectric conversion sensitivity and an excellent frequency characteristic at the same time.
摘要翻译：由于光电二极管的PN结由具有低杂质浓度和外延层的硅衬底形成，所以PN结中的耗尽层的宽度被形成得更宽，结电容的寄生电容降低，扩散硅衬底的长度形成得更长。此外，通过高能离子注入方法形成含有高杂质浓度的掩埋层，使得埋入层不能被施加到PN结的反向电压消耗，这被用作引出区域阳极，因此导致阳极处的低寄生电阻。由此，本发明提供了一种半导体器件，其包括同时实现高光电转换灵敏度和优异频率特性的光电检测器及其制造方法。

74. 发明授权

US6146956A PNP lateral bipolar electronic device and corresponding manufacturing process 失效
公开(公告)号：US6146956A
公开(公告)日：2000-11-14
申请号：US87397
申请日：1998-05-29
申请人： Angelo Pinto , Carlo Alemanni
发明人： Angelo Pinto , Carlo Alemanni
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L29/735 , H01L21/8222
CPC分类号： H01L29/6625 , H01L21/8228 , H01L27/082 , H01L29/735
摘要： The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

75. 发明授权

US5686322A Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
公开(公告)号：US5686322A
公开(公告)日：1997-11-11
申请号：US775361
申请日：1997-01-03
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L21/265
CPC分类号： H01L27/0826 , H01L21/8228 , H01L27/082
摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device. Each device is then doped with the second type impurity through the second mask. The use of the high diffusion coefficient layer in the base contact enables the base dopant to spread laterally from the edge contact to the region where the base poly is in contact with the collector, with the same diffusion cycle that is used for the emitter.

76. 发明申请

US20180090506A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20180090506A1
公开(公告)日：2018-03-29
申请号：US15713926
申请日：2017-09-25
申请人： SII Semiconductor Corporation
发明人： Kazuhiro TSUMURA
IPC分类号： H01L27/11521 , H01L27/112 , H01L21/8228 , G11C16/02 , G11C17/18 , H01L29/94 , H01L29/423
CPC分类号： H01L27/11521 , G11C16/02 , G11C17/08 , G11C17/18 , H01L21/8228 , H01L27/11206 , H01L29/42324 , H01L29/94
摘要： Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.

77. 发明申请

US20170236824A1 COMPLEMENTARY BIPOLAR SRAM 有权
公开(公告)号：US20170236824A1
公开(公告)日：2017-08-17
申请号：US15581646
申请日：2017-04-28
申请人： International Business Machines Corporation
发明人： Tak H. Ning
IPC分类号： H01L27/102 , H01L21/8229 , H01L21/8228 , G11C11/416 , G11C11/411
CPC分类号： G11C11/416 , G11C11/411 , G11C11/4116 , H01L21/8228 , H01L21/8229 , H01L27/1025 , H01L27/11
摘要： A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

78. 发明申请

US20170110450A1 COMPLEMENTARY SOI LATERAL BIPOLAR TRANSISTORS WITH BACKPLATE BIAS 有权
公开(公告)号：US20170110450A1
公开(公告)日：2017-04-20
申请号：US15278459
申请日：2016-09-28
申请人： International Business Machines Corporation
发明人： Tak H. Ning , Jeng-Bang Yau
IPC分类号： H01L27/082 , H01L27/12 , H01L21/84 , H01L21/8228
CPC分类号： H01L27/082 , H01L21/76264 , H01L21/8228 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0821 , H01L29/1008 , H01L29/66242 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/737
摘要： A method for fabricating a complementary bipolar junction transistor (BJT) integrated structure. The method includes forming a first backplate in a monolithic substrate below a first buried oxide (BOX) layer. Another forming step forms a second backplate in the monolithic substrate below the first BOX layer. The second backplate is electrically isolated from the first backplate. Another forming step forms an NPN lateral BJT above the first BOX layer and superposing the first backplate. The NPN lateral BJT is configured to conduct electricity horizontally between an NPN emitter and an NPN collector when the NPN lateral BJT is active. Another forming step forms a PNP lateral BJT superposing the second backplate. The PNP lateral BJT is configured to conduct electricity horizontally between a PNP emitter and a PNP collector when the PNP lateral BJT is active.

79. 发明授权

US09577063B2 Bipolar transistor, band-gap reference circuit and virtual ground reference circuit and methods of fabricating thereof 有权
标题翻译：双极晶体管，带隙参考电路和虚拟接地参考电路及其制造方法
公开(公告)号：US09577063B2
公开(公告)日：2017-02-21
申请号：US15088961
申请日：2016-04-01
申请人： Semiconductor Manufacturing International (Beijing) Corporation
发明人： Min-Hwa Chi , Lihying Ching , Deyuan Xiao
IPC分类号： H01L29/66 , G05F3/30 , H01L21/8228 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/73 , H01L21/265 , H01L29/08 , H01L29/10 , H01L29/739 , H03K17/60 , H01L29/06
CPC分类号： H01L29/66325 , G05F3/30 , H01L21/26586 , H01L21/8228 , H01L21/84 , H01L27/082 , H01L27/1203 , H01L29/063 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/1095 , H01L29/66265 , H01L29/7317 , H01L29/7393 , H03K17/60
摘要： The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact to the base.
摘要翻译：本发明提供一种双极晶体管，双极型晶体管的形成方法，双极型晶体管的导通方法，带隙基准电路，虚拟接地参考电路以及双极性晶体管的双带隙基准电路。双极晶体管包括：绝缘体上硅晶片; 基极区域，发射极区域和集电极区域; 位于顶部硅层上的基极区电介质层，并在基底区域顶部; 基区栅极电介质层上的基区控制栅极; 经由第一触点连接到发射极区域的发射极; 集电极，经由第二触点连接到集电区; 以及通过第三触点连接到基区控制门的基区控制栅电极。形成双极晶体管的工艺与传统的标准CMOS工艺完全兼容; 并且用于导通双极晶体管的基极电流基于GIDL电流并且通过向基极区域控制栅电极施加电压而形成，而不需要与基极接触。

80. 发明授权

US09337324B2 Bipolar transistor, band-gap reference circuit and virtual ground reference circuit 有权
标题翻译：双极晶体管，带隙参考电路和虚拟接地参考电路
公开(公告)号：US09337324B2
公开(公告)日：2016-05-10
申请号：US14463583
申请日：2014-08-19
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
发明人： Min-Hwa Chi , Lihying Ching , Deyuan Xiao
IPC分类号： H01L21/8228 , H01L29/739 , G05F3/30 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/66 , H01L29/73 , H01L21/265 , H01L29/08 , H01L29/10 , H03K17/60
CPC分类号： H01L29/66325 , G05F3/30 , H01L21/26586 , H01L21/8228 , H01L21/84 , H01L27/082 , H01L27/1203 , H01L29/063 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/1095 , H01L29/66265 , H01L29/7317 , H01L29/7393 , H03K17/60
摘要： The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact to the base.
摘要翻译：本发明提供一种双极晶体管，双极型晶体管的形成方法，双极型晶体管的导通方法，带隙基准电路，虚拟接地参考电路以及双极性晶体管的双带隙基准电路。双极晶体管包括：绝缘体上硅晶片; 基极区域，发射极区域和集电极区域; 位于顶部硅层上的基极区电介质层，并在基底区域顶部; 基区栅极电介质层上的基区控制栅极; 经由第一触点与发射极区域连接的发射极; 集电极，经由第二触点连接到集电区; 以及通过第三触点连接到基区控制门的基区控制栅电极。形成双极晶体管的工艺与传统的标准CMOS工艺完全兼容; 并且用于导通双极晶体管的基极电流基于GIDL电流并且通过向基极区域控制栅电极施加电压而形成，而不需要与基极接触。

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