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    • 77. 发明授权
    • Reduced-power programming of multi-level cell (MLC) memory
    • 多级单元(MLC)存储器的低功耗编程
    • US08014196B2
    • 2011-09-06
    • US12200129
    • 2008-08-28
    • Nils Graef
    • Nils Graef
    • G11C16/06G11C16/10G11C16/12G11C16/26
    • G11C7/1006G11C11/5628G11C2211/5622
    • In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log2 m) MLCs are used to store the p-symbol codeword (iii) each MLC stores one symbol of the codeword. The energy-saving decoder is adapted to read p-symbol codewords from the MLC NAND flash memory and decode each p-symbol codeword into a k-bit segment of raw user data for provision to the host controller. The host controller is adapted to vary k and n to conserve usage of power or memory-space, as needed.
    • 在一个实施例中,移动电子设备具有主机控制器,节能编码器,节能解码器和多电平单元(MLC)NAND闪速存储器。 主机控制器以k位分段向节能编码器提供原始用户数据。 节能编码器将每个k比特段编码为编码用户数据的n比特段,用于将MLC NAND闪存编程为p符号码字,其中(i)k小于n(ii)p(= n / log2 m)MLC用于存储p符号码字(iii),每个MLC存储码字的一个符号。 节能解码器适于从MLC NAND闪速存储器读取p符号码字,并将每个p符号码字解码为原始用户数据的k比特段以提供给主机控制器。 主机控制器适于根据需要改变k和n以节省功率或存储空间的使用。
    • 79. 发明授权
    • Semiconductor memory device and write method thereof
    • 半导体存储器件及其写入方法
    • US07796439B2
    • 2010-09-14
    • US12017543
    • 2008-01-22
    • Fumitaka AraiTakeshi KamigaichiAtsuhiro Sato
    • Fumitaka AraiTakeshi KamigaichiAtsuhiro Sato
    • G11C11/34G11C11/06
    • G11C16/0483G11C11/5628G11C16/3454G11C16/3459G11C2211/5621G11C2211/5622G11C2211/5642
    • A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
    • 半导体存储器件包括存储单元阵列,位线,源极线,读出放大器,数据缓冲器,电压产生电路和控制电路,该控制电路被配置为使得控制电路分批写入写数据 在位线的多个存储单元中,控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据,并且控制电路执行从存储器单元的验证读取,并执行 在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下,对多个存储器中的保持的写入数据进行分批写入 细胞再次。