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71. 发明授权

EP0251588B1 Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses 失效转让
标题翻译：提供用于通讯设备的字节同步的双向交互多路复用器系统
公开(公告)号：EP0251588B1
公开(公告)日：1993-09-01
申请号：EP87305427.4
申请日：1987-06-18
申请人： GENERAL DATACOMM, INC.
发明人： Manning, David J.
IPC分类号： H04J3/12
CPC分类号： G06F5/10 , H04J3/12 , H04J3/1682 , H04Q2213/13166 , H04Q2213/13174 , H04Q2213/13292 , H04Q2213/13332

72. 发明公开

EP0542881A1 APPARATUS AND METHOD FOR DETERMINING LINE RATES 失效
标题翻译：方法和系统测定的传输速率。
公开(公告)号：EP0542881A1
公开(公告)日：1993-05-26
申请号：EP91915573.0
申请日：1991-07-22
申请人： General DataComm, Inc.
发明人： GHELBERG, Emil , EVANS, Patrick, A. , LEE, Seng, Poh , LIYANAGE, Don, W.
IPC分类号： H04L25
CPC分类号： H04L25/0262
摘要： Un appareil et des procédés destinés à déterminer automatiquement le débit binaire d'un signal d'arrivée sont décrits. L'appareil comprend un compteur (30), un circuit logique (20) et un circuit générant un histogramme (45). Le compteur (30) compte le nombre de cycles rapides d'horloge de référence qui tiennent dans chaque impulsion du signal d'arrivée pour un nombre statistiquement significatif d'impulsions et fournit des indications relatives à ce nombre au circuit logique (20). Le circuit logique (20) associe chacune des indications avec l'un des débits binaires permissibles d'une multiplicité de débits binaires permissibles. Le circuit générant l'histogramme (45) recherche le nombre de fois que les nombres évalués sont associés à chaque débit binaire permissible. Selon un mode de réalisation, le débit binaire permissible le plus souvent choisi est choisi comme le débit binaire du signal d'arrivée. Selon un autre mode de réalisation, si un débit de ligne DDS1 est déterminé comme étant le débit binaire le plus souvent choisi, le débit de DDS2 associé au débit de ligne DDS1 est provisoirement choisi. De plus, si un débit de ligne DDS2 est déterminé comme étant le débit binaire le plus souvent choisi, le débit de ligne DDS2 est provisoirement choisi.

73. 发明公开

EP0373755A3 FRAMING ALGORITHMS MINIMIZING CHANNEL EXCURSION 失效
标题翻译：最小化通道速度的框架算法
公开(公告)号：EP0373755A3
公开(公告)日：1991-08-07
申请号：EP89310626
申请日：1989-10-17
申请人： GENERAL DATACOMM, INC.
发明人： BAINS, KULDIP S. , GORDON, DAVID P.
IPC分类号： H04J3/16
CPC分类号： H04J3/1682
摘要： Algorithms for ordering selects for a plurality of channels to be multiplexed into a frame so as to minimize or reduce channel excursion are provided. The channel select position counter for each of the channels to be multiplexed are initialized. In one embodiment, the first and succeeding channel selects are chosen based on the lowest price (highest cost) ready channel, with the price of a channel being equal to the value of the channel select position counter divided by the number of selects for that channel in the frame, and the readiness of the channel being indicated either by an indicator, or by the relative value of the position counter to the initial value of the position counter. After a select is made, the position counter of the selected channel is increased by the total number of selects in the frame, and the position counters of all of the channels, including the selected channel are decremented by a value corresponding to the number of selects for that channel in the frame. After such updating, another selection for the frame may be based on the lowest priced ready channel. In a second embodiment, the first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relatively lower value. Where channel ready counter integer values of more than one channel are equal, the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is decremented by a value corresponding to the number of selects for that channel in the frame. If the position counter of a channel reach zero or goes negative as a result of the decrementing, the position counter of that channel is increased by the total number of selects in the frame, and the ready counter for that channel is incremented by one.

74. 发明公开

EP0365265A3 FRAMING ALGORITHM FOR BIT INTERLEAVED TIME DIVISION MULTIPLEXER 失效
标题翻译：用于位交互时间段多路复用器的框架算法
公开(公告)号：EP0365265A3
公开(公告)日：1991-08-07
申请号：EP89310628
申请日：1989-10-17
申请人： GENERAL DATACOMM, INC.
发明人： BAINS, KULDIP S.
IPC分类号： H04J3/16
CPC分类号： H04J3/1629
摘要： Methods are provided for multiplexing a plurality of channels onto a sub-aggregate of and aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACS compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S)F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame. Where different primary frame rates may be used, the sum of (A/P) plus (P/S)F1 plus (S/T)F2 is minimized to find primary and secondary frame rates which will permit an optimally small total frame length, given the sub-aggregate rate A.

75. 发明公开

EP0340014A2 Adaptive multiharmonic phase jitter compensation 失效
标题翻译：自适应康复多功能振荡器。
公开(公告)号：EP0340014A2
公开(公告)日：1989-11-02
申请号：EP89304246.5
申请日：1989-04-27
申请人： General DataComm, Inc.
发明人： Goldstein, Yuri
IPC分类号： H04L27/06 , H04L27/22
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0069
摘要： A multiharmonic adaptive phase jitter compensator for a high speed modem is provided. The compensator includes an IIR filter for each harmonic of phase jitter for which compensation is desired. The coefficent update of each IIR filter as well as the input to the primary jitter frequency IIR receives identical information from a phase detector which compares an equalized phase corrected signal entering a decision means with the ideal point determined by the decision means. However, the IIRs for the higher harmonics are trained with different information. Thus, the primary jitter frequency as adaptively determined by the first IIR is fed to harmonic computation circuitry. The harmonic computation circuitry then provides an adapted second harmonic to the second harmonic IIR, and adapted third harmonic to the third harmonic IIR, etc. The outputs of all the IIRs are summed, and the cosine and sine of the sum are provided to phase correct the equalized signal before it enters the decision circuitry.
摘要翻译：提供了一种用于高速调制解调器的多谐波自适应相位抖动补偿器。补偿器包括用于需要补偿的相位抖动的每个谐波的IIR滤波器。每个IIR滤波器的系统更新以及主抖动频率IIR的输入从相位检测器接收相同的信息，该相位检测器将进入判定装置的均衡相位校正信号与由判定装置确定的理想点进行比较。然而，高次谐波的二次谐波被不同的信息训练。因此，由第一IIR自适应地确定的主抖动频率被馈送到谐波计算电路。谐波计算电路然后向第二谐波IIR提供适应的二次谐波，并且对三次谐波IIR等进行适配的三次谐波。将所有IIR的输出相加，并将和的余弦和正弦提供给相位校正均衡信号进入判定电路之前。

76. 发明授权

US6067286A Data network switch with fault tolerance 失效
标题翻译：数据网络交换机具有容错能力
公开(公告)号：US6067286A
公开(公告)日：2000-05-23
申请号：US930973
申请日：1997-10-07
申请人： Trevor Jones , Richard Barnett
发明人： Trevor Jones , Richard Barnett
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/26
CPC分类号： H04L49/153 , H04Q11/0478 , H04L2012/5627
摘要： An ATM data network switch having two separate but simultaneously active switch fabrics and a plurality of slot controllers is disclosed. Each slot controller has at least one external data link thereto and is separately connected to the two separate switch fabrics. Each switch fabric was the ability to switch a data cell transmitted from any one of the slot controllers to any of the other slot controllers. Each slot controller is arranged to determine the availability of the data paths to all the other slot controllers through both switch fabrics and to select for each cell to be switched a data path through one or the other of the switch fabric according to the availability determined.
摘要翻译： PCT No.PCT / US96 / 05029 Sec。 371日期1997年10月7日第 102（e）日期1997年10月7日PCT 1996年4月9日PCT PCT。公开号WO96 / 32790 日期1996年10月17日公开了一种具有两个单独但同时有效的交换结构和多个时隙控制器的ATM数据网络交换机。每个时隙控制器具有至少一个外部数据链路，并分别连接到两个分开的交换结构。每个交换结构是将从任一个时隙控制器发送的数据信元切换到任何其他时隙控制器的能力。每个时隙控制器被布置成通过两个交换结构来确定到所有其他时隙控制器的数据路径的可用性，并且根据所确定的可用性来选择要切换数据路径通过交换结构中的一个或另一个的每个小区。

77. 发明授权

US5933417A Multimedia multipoint telecommunications reservation acceptance systems and controllers 失效
标题翻译：多媒体多点电信预约接收系统和控制器
公开(公告)号：US5933417A
公开(公告)日：1999-08-03
申请号：US877463
申请日：1997-06-16
申请人： Sunil Rottoo
发明人： Sunil Rottoo
IPC分类号： H04L12/18 , H04L12/56 , H04M3/56 , H04N7/15 , H04M3/42
CPC分类号： H04L12/1877 , H04M3/567 , H04N7/152 , H04M3/565
摘要： A multimedia conference reservation controller and reservation acceptance system includes a database of all presently reserved resources on each MMS controlled by the reservation controller which includes an identification of each resource together with the starting time and ending time of the reservation. The acceptance system is designed to accept a reservation query which includes a list of required resources and a list of flexible resources, where flexible resource are considered desirable resources, but not absolutely necessary resources. In response to a reservation query involving a single MMS, the acceptance system accesses the database and builds a list of resources together with the times during which those resources are already reserved. This list is used to create a Resource Availability Matrix which is then analyzed and a list of time periods is generated during which the requested resources are available. In addition, the matrix analysis also indicates exactly which resources must be used to satisfy the request for each time period. In response to a reservation query involving two MMS units, the acceptance system builds two resource availability matrices, one for each MMS which are analyzed to generate a list indicating the time periods during which the conference can be reserved and the resources which must be used.
摘要翻译：多媒体会议预约控制器和预约接收系统包括由预留控制器控制的每个MMS上的所有当前预留资源的数据库，其包括每个资源的标识以及预约的开始时间和结束时间。接受系统被设计为接受包括所需资源的列表和灵活资源的列表的预留查询，其中灵活资源被认为是期望的资源，但不是绝对必要的资源。响应涉及单个MMS的预约查询，接受系统访问数据库并建立资源列表以及这些资源已经保留的时间。该列表用于创建资源可用性矩阵，然后分析资源可用性矩阵，并且生成所请求的资源可用的时间段列表。此外，矩阵分析还准确地指出了哪些资源必须用于满足每个时间段的请求。响应于涉及两个MMS单元的预留查询，接受系统构建两个资源可用性矩阵，每个MMS被分析一个，以生成指示可以保留会议的时间段的列表以及必须使用的资源。

78. 发明授权

US5822371A Mapper for high data rate signalling 失效
标题翻译：用于高数据速率信号的映射器
公开(公告)号：US5822371A
公开(公告)日：1998-10-13
申请号：US801066
申请日：1997-02-14
申请人： Yuri Goldstein , Yuri Okunev
发明人： Yuri Goldstein , Yuri Okunev
IPC分类号： H03M7/00 , H04B14/02 , H04B14/04 , H04L25/49 , H04L27/00 , H04L27/02 , H04L27/34
CPC分类号： H04L27/3411 , H04B14/023 , H04B14/048 , H04L25/4927
摘要： A pulse amplitude modulated (PAM) mapper includes a constellation matrix memory which stores indications of a plurality of different constellations, wherein at least one of the different stored constellations is of different dimension than another of the stored constellations. The constellations are used individually or together to support a plurality of different modem data rates. In a preferred embodiment, in addition to the constellation matrix memory, the mapper includes a logic block, a constellation controller, a PAM code generation block, and an output register. The logic block receives incoming bits of information, groups the bits as a function of the desired or agreed upon bit rate as indicated by the constellation controller, and provides a plurality of each group of bits to the PAM code generation block, and one or more sign bits to the output register. The PAM code generation block uses the provided bits to choose at least one point from one of the constellations, and uses each chosen constellation point to generate a seven-bit PAM code (typically .mu.-law or A-law code value) word. Each seven-bit output is provided to the output register, and together with associated sign bits generates output bytes. Algorithms are provided for choosing multiple points from the 2D and higher dimensional constellations from provided groups of bits.
摘要翻译：脉冲幅度调制（PAM）映射器包括存储多个不同星座的指示的星座矩阵存储器，其中不同存储的星座中的至少一个与所存储的星座中的另一个具有不同的维度。星座单独或一起用于支持多种不同的调制解调器数据速率。在优选实施例中，除了星座矩阵存储器之外，映射器包括逻辑块，星座控制器，PAM码生成块和输出寄存器。逻辑块接收输入的信息比特，将比特分组为由星座控制器指示的所需或约定的比特率的函数，并且向PAM码生成块提供多个每组比特，并且提供一个或多个符号位到输出寄存器。 PAM代码生成块使用提供的位从一个星座中选择至少一个点，并使用每个选择的星座点来生成七位PAM码（通常为μ-或A律代码值）字。每个七位输出都提供给输出寄存器，与相关的符号位一起生成输出字节。提供算法用于从提供的位组的2D和更高维度星座中选择多个点。

79. 发明授权

US5818884A High speed synchronous digital data bus system having unterminated data and clock buses 失效
标题翻译：具有无终止数据和时钟总线的高速同步数字数据总线系统
公开(公告)号：US5818884A
公开(公告)日：1998-10-06
申请号：US411343
申请日：1995-03-27
申请人： Welles Reymond
发明人： Welles Reymond
IPC分类号： G06F1/04 , G06F1/10 , G06F13/40 , H03L7/081 , H04J3/06 , H04L7/00
CPC分类号： G06F1/10 , G06F13/4072 , H03L7/0812 , H04L7/0008 , H04L2007/047
摘要： A high speed synchronous digital bidirectional data bus system is provided and includes an M-bit unterminated data bus, an unterminated standing sine wave clock bus, and a plurality of integrated circuit bus interfaces. Each IC bus interface is preferably substantially incorporated on a single CMOS LSI chip and includes M bus drivers with associated send data logic, M data receivers with associated receive data logic, and a clock receiver. The output currents of the bus drivers on all of the chips are preferably stabilized so that each driver drives the bus at substantially the same output current. The drivers are preferably complementary polar driven CMOS logic elements. For this case, for each data receiver, a bus keeper is coupled to the output and the input of the bus receiver to maintain the last state of the data bus. In addition, the clock receivers and the data receivers are embodied as high speed comparators having internal hysteresis. The clock receivers are preferably provided with a delay generator which produces a "guard band" during which the bus drivers are tri-stated before they can drive the data bus. This prevents conflicts on the bus and guarantees end sampling of data.
摘要翻译：提供了一种高速同步数字双向数据总线系统，包括M位未终端数据总线，未终端正弦波时钟总线和多个集成电路总线接口。每个IC总线接口优选地基本上结合在单个CMOS LSI芯片上，并且包括具有相关联的发送数据逻辑的M总线驱动器，具有相关联的接收数据逻辑的M个数据接收器和时钟接收器。所有芯片上的总线驱动器的输出电流优选地是稳定的，使得每个驱动器以基本上相同的输出电流驱动总线。驱动器优选地是互补极性驱动的CMOS逻辑元件。对于这种情况，对于每个数据接收器，总线保护器耦合到总线接收器的输出和输入以保持数据总线的最后状态。此外，时钟接收器和数据接收器被实现为具有内部滞后的高速比较器。时钟接收器优选地设置有延迟发生器，其产生“保护带”，在该保护带期间，总线驱动器在它们可以驱动数据总线之前是三态的。这可以防止总线上的冲突，并保证数据的最终采样。

80. 发明授权

US5712853A Apparatus and method for transferring operation, administration and management cells across and ATM data frame user network interface 失效
标题翻译： ATM和ATM数据帧用户网络接口传输操作，管理和管理单元的设备和方法
公开(公告)号：US5712853A
公开(公告)日：1998-01-27
申请号：US526846
申请日：1995-09-11
申请人： Deepak Mathur , Peter T. Marino
发明人： Deepak Mathur , Peter T. Marino
IPC分类号： H04L12/56 , H04Q11/04 , H04J3/16
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5625 , H04L2012/5652
摘要： A method and switch appratus for transporting an ATM layer OAM cell across a FUNI are disclosed. The method broadly includes generating a DXI (FUNI) frame from the ATM layer OAM cell by using certain bits of the five byte ATM overhead as bits in the two byte DXI (FUNI) header, using the forty-eight byte ATM OAM cell payload as the payload for the DXI (FUNI) frame, and providing an indication in a predetermined bit field of the two byte DXI header that the forty-eight byte payload is an ATM OAM cell. Preferably, the predetermined bit field includes the previously reserved second lsb of Octet 1 of the DXI frame header, and the previously reserved third lsb of Octet 2 of the DXI frame header, which are set to values of "0" and "1" to indicate an ATM OAM cell, and to "0" and "0" to identify "regular" data.
摘要翻译：公开了一种用于在FUNI上传输ATM层OAM单元的方法和切换设备。该方法广泛地包括通过使用四字节的ATM OAM信元有效载荷作为两字节DXI（FUNI）报头中的位，通过使用五字节ATM开销的某些位来从ATM层OAM信元生成DXI（FUNI）帧用于DXI（FUNI）帧的有效载荷，并且在四字节有效载荷是ATM OAM信元的两个字节DXI报头的预定位字段中提供指示。优选地，预定比特字段包括DXI帧头部的Octet1的先前保留的第二个lsb和DXI帧头部的先前保留的Octet 2的第三个lsb，它们被设置为“0”和“1”到指示ATM OAM小区，并且指示“0”和“0”来标识“正常”数据。

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