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    • 75. 发明申请
    • PROTEIN HAVING SWEETNESS
    • 有蛋白质的蛋白质
    • US20100040754A1
    • 2010-02-18
    • US12532716
    • 2008-01-28
    • Keiko AbeKenichiro NakajimaTomiko AsakuraTakumi MisakaSho Ishii
    • Keiko AbeKenichiro NakajimaTomiko AsakuraTakumi MisakaSho Ishii
    • C12N5/10C07K14/00C12N15/11C12N15/00A23L1/236
    • C07K14/415A23L27/31C07K14/43
    • An object of the present invention is to discover a substance with sweetness independent of pH and to provide a novel composition with sweetness characterized by containing the substance. Provided are: an NAS variant characterized by having sweetness independent of pH in the case of combination with a polypeptide NBS variant by causing substitution mutation or deletion mutation in one or several amino acids out of the amino acid residues constituting a polypeptide NAS; an NBS variant characterized by having sweetness independent of pH in the case of combination with a polypeptide NAS variant by causing substitution mutation or deletion mutation in one or several amino acids out of the amino acid residues constituting a polypeptide NBS; a diner comprising a combination of the NAS variant and the NBS variant; a recombinant vector containing a gene encoding the NAS variant and a gene encoding the NBS variant; and a transformant containing the vector.
    • 本发明的目的是发现与pH无关的甜味物质,并提供具有特征在于含有该物质的甜味的新型组合物。 提供:NAS变体,其特征在于通过在构成多肽NAS的氨基酸残基中的一个或几个氨基酸中引起取代突变或缺失突变,在与多肽NBS变体组合的情况下具有与pH无关的甜度; 在通过在构成多肽NBS的氨基酸残基中的一个或几个氨基酸中引发取代突变或缺失突变而与多肽NAS变体组合的情况下,其特征在于具有独立于pH的甜度的NBS变体; 包括NAS变体和NBS变体的组合的餐具; 包含编码NAS变体的基因和编码NBS变体的基因的重组载体; 和含有载体的转化体。
    • 78. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • 半导体集成电路
    • US20090217222A1
    • 2009-08-27
    • US12211842
    • 2008-09-17
    • Shinichi YasudaKumiko NomuraKeiko Abe
    • Shinichi YasudaKumiko NomuraKeiko Abe
    • G06F17/50
    • G06F11/006G06F11/2242
    • A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes.
    • 半导体集成电路包括:多个处理器元件,每个处理器元件包括测试电路,该测试电路测试处理器元件中是否存在故障并输出测试结果; 设置为分别与处理器元件相关联的多个开关盒,每个开关盒被配置为具有用于存储另一个处理器元件的信息的表格,并且基于存储的信息将相应的处理器元件的信息发送到另一个处理器元件 在桌子上 设置为分别与处理器元件相关联的多个识别电路,每个识别电路被配置为基于测试的结果和缺陷处理器元件的输出位置信息来识别有缺陷的处理器元件; 以及发送电路,被配置为将从识别电路输出的缺陷处理器元件的位置信息发送到开关盒。