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71. 发明申请

US20100142271A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE 有权
标题翻译：可预防阈值电压转换的半导体存储器件
公开(公告)号：US20100142271A1
公开(公告)日：2010-06-10
申请号：US12538290
申请日：2009-08-10
申请人： Mitsuaki HONMA , Noboru Shibata
发明人： Mitsuaki HONMA , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/06
摘要： A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels.
摘要翻译：存储单元阵列连接到字线和位线，并且被配置为使得在一个存储单元中存储n个电平（n是大于4的自然数）的一个电平的多个存储单元被排列成矩阵。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路将对应于写入数据的写入电压施加到存储单元。每个写入数据的写入电压不同。在写入电压施加操作相对于所有n个电平结束之后，对每个写入数据执行验证操作。

72. 发明授权

US07679959B2 Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages 有权
标题翻译：产生对应于多个阈值电压的电压的半导体存储器件
公开(公告)号：US07679959B2
公开(公告)日：2010-03-16
申请号：US12276957
申请日：2008-11-24
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3454 , G11C2211/5621
摘要： A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section. A voltage generating circuit generates a voltage on the basis of the voltage data generated by the arithmetic circuit. The arithmetic circuit, when reading data from the memory cell at threshold level k (k
摘要翻译：存储单元MC使用阈值级别1,2存储多位数据。。。，n（n是自然数）。存储部存储用于生成阈值电平的多个参数数据项。算术电路通过累加从存储部读取的参数数据，生成用于产生与阈值电平对应的电压的电压数据。电压产生电路根据由运算电路产生的电压数据产生电压。算术电路在阈值电平k（k <= n）下从存储单元读取数据时，通过在阈值电平i至k（i <= k）下累积参数数据来产生电压数据。

73. 发明申请

US20090316479A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE 有权
标题翻译：可降低写电压的半导体存储器件
公开(公告)号：US20090316479A1
公开(公告)日：2009-12-24
申请号：US12407295
申请日：2009-03-19
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage
摘要翻译：存储单元阵列被配置为使得存储n值（n是大于2的自然数）的一个值的多个存储单元被布置成矩阵。控制电路根据输入数据控制字线和位线的电压。控制电路在写操作中将第一电压提供给所选单元的字线，并将第二电压提供给与所选单元相邻的至少一个字线。此后，控制电路将与所选择的单元相邻的至少一个字线的电压从第二电压改变为第三电压（第二电压<第三电压），并且还改变所选单元的字线的电压从第一电压到第四电压（第一电压<第四电压）。

74. 发明授权

US07573750B2 High-speed verifiable semiconductor memory device 有权
标题翻译：高速可验证半导体存储器件
公开(公告)号：US07573750B2
公开(公告)日：2009-08-11
申请号：US12210585
申请日：2008-09-15
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3436 , G11C16/3404
摘要： A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
摘要翻译：存储单元使用n（n：自然数大于1）阈值电压存储多个数据。在验证存储器单元是否达到预定阈值电压的验证操作中，电压供应电路向存储器单元的栅极提供预定电压。连接到存储器单元的一个端子的检测电路将存储器单元的一个端子充电到预定电位。检测电路基于第一检测定时检测存储单元的一个端子的电压，并且还基于第二检测定时检测存储单元的一个端子的电压。

75. 发明申请

US20090190399A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY 有权
标题翻译：可修正读取电平的半导体存储器件
公开(公告)号：US20090190399A1
公开(公告)日：2009-07-30
申请号：US12416750
申请日：2009-04-01
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

76. 发明授权

US07525839B2 Semiconductor memory device capable of correcting a read level properly 有权
标题翻译：能够正确地校正读取电平的半导体存储器件
公开(公告)号：US07525839B2
公开(公告)日：2009-04-28
申请号：US11753143
申请日：2007-05-24
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

77. 发明授权

US07483304B2 Semiconductor memory device capable of setting a negative threshold voltage 有权
标题翻译：能够设定负阈值电压的半导体存储器件
公开(公告)号：US07483304B2
公开(公告)日：2009-01-27
申请号：US12055074
申请日：2008-03-25
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3454
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。控制电路控制字线和位线的电位。控制电路当从连接到第一位线的存储单元读取数据时，将第一电压提供给位于第一位线旁边的第二位线和存储单元阵列的源极线。

78. 发明授权

US07443734B2 Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data 有权
标题翻译：具有电压产生电路的半导体存储器件，其使用少量数据产生多个电压
公开(公告)号：US07443734B2
公开(公告)日：2008-10-28
申请号：US11531920
申请日：2006-09-14
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C8/08 , G11C16/0483 , G11C16/3459
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。存储部存储对应于第一写入操作的写入电压的初始值和用于校正写入电压的校正值。电压产生电路基于存储在存储部中的写入电压的初始值和校正值，在第一写入操作或第二写入操作中产生字线写入电压。

79. 发明授权

US07394695B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US07394695B2
公开(公告)日：2008-07-01
申请号：US11511488
申请日：2006-08-29
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

80. 发明授权

US07394691B2 Semiconductor memory device which prevents destruction of data 有权
标题翻译：防止数据破坏的半导体存储器件
公开(公告)号：US07394691B2
公开(公告)日：2008-07-01
申请号：US11498142
申请日：2006-08-03
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34 , G11C7/00 , G11C29/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483
摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.
摘要翻译：每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。每个存储单元通过第一写操作和第二写操作来存储n值数据。读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。

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