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71. 发明授权

US06255734B1 Passivated copper line semiconductor device structure 有权
标题翻译：钝化铜线半导体器件结构
公开(公告)号：US06255734B1
公开(公告)日：2001-07-03
申请号：US09670325
申请日：2000-09-27
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L2348
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu3Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.
摘要翻译：一种形成用于薄膜电子器件的铜导体的方法包括：在导体上形成层叠在衬底顶部以上的阻挡层堆叠，在阻挡层顶部的铜层和顶部的硬掩模层的铜层。在硬掩模层的顶部上形成掩模，并通过将层压蚀成形成铜层的掩模的侧面上的衬底到铜导体线中并且使铜导体线的侧壁露出而形成叠层。生长铜锗化合物（Cu3Ge）化合物钝化层仅选择性地生长在铜导线的侧壁上。

72. 发明授权

US06221758B1 Effective diffusion barrier process and device manufactured thereby 有权
公开(公告)号：US06221758B1
公开(公告)日：2001-04-24
申请号：US09225064
申请日：1999-01-04
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76805 , H01L21/76843
摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

73. 发明授权

US06207568B1 Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer 有权
标题翻译：用于形成（111）取向的含铝导体层的电离金属等离子体（IMP）方法
公开(公告)号：US06207568B1
公开(公告)日：2001-03-27
申请号：US09200554
申请日：1998-11-27
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76841 , H01L21/2855 , H01L21/28568 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.
摘要翻译：一种形成含铝导体层的方法。首先提供基板。然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。最后，在钛层上形成含有铝的导体层。通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

74. 发明授权

US06191025B1 Method of fabricating a damascene structure for copper medullization 有权
标题翻译：制造铜镶嵌镶嵌结构的方法
公开(公告)号：US06191025B1
公开(公告)日：2001-02-20
申请号：US09349847
申请日：1999-07-08
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76801 , H01L21/76802 , H01L21/76832
摘要： A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited. Trenches are then etched in the fourth dielectric using the second dielectric, which has been maintained intact by the sacrificial third dielectric, as an etch stop. The trenches are then filled with a second barrier metal and second conductor metal. Excess second barrier metal and second conductor metal are then removed using chemical mechanical polishing to complete the damascene structure.
摘要翻译：一种制造铜导体镶嵌结构的方法。在其上形成有器件的硅衬底上形成第一，第二和第三电介质层。第二电介质将随后作为蚀刻停止。第三电介质是用于保护第二电介质的牺牲层。然后在第一，第二和第三电介质的层中蚀刻接触孔。然后沉积第一阻挡金属和第一导体金属，填充接触孔。然后使用诸如化学机械抛光的方法将第一阻挡金属和第一导体金属去除到第三电介质层的原始顶表面和第二电介质的顶表面之间的水平。牺牲的第三绝缘体在化学机械抛光期间保护第二电介质层。然后沉积第四电介质层。然后使用已被牺牲的第三电介质保持的第二电介质作为蚀刻停止层，在第四电介质中蚀刻沟槽。然后用第二阻挡金属和第二导体金属填充沟槽。然后使用化学机械抛光去除过量的第二阻挡金属和第二导体金属，以完成镶嵌结构。

75. 发明授权

US6130157A Method to form an encapsulation layer over copper interconnects 有权
标题翻译：在铜互连上形成封装层的方法
公开(公告)号：US6130157A
公开(公告)日：2000-10-10
申请号：US356005
申请日：1999-07-16
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76849 , H01L21/76879
摘要： A method to form copper interconnects with an improved encapsulation layer is achieved. A substrate layer is provided. Conductive traces are provided overlying the substrate layer. A first intermetal dielectric layer is deposited overlying the conductive traces. The first intermetal dielectric layer is etched through to the underlying conductive traces where the first intermetal dielectric layer is not protected by a photoresist mask to form interconnect trenches. A barrier layer is deposited overlying the first intermetal dielectric layer and exposed the conductive traces. A copper layer is deposited overlying the barrier layer and filling the interconnect trenches. The copper layer and the barrier layer are polished down to the top surface of the first intermetal dielectric layer to define copper interconnects. An encapsulation layer is formed overlying the copper interconnects wherein the encapsulation layer is not formed overlying the first intermetal interconnect layer and wherein the encapsulation layer is at least partially comprised of tungsten nitride. A second intermetal dielectric layer is deposited and the fabrication of the integrated circuit device is completed.
摘要翻译：实现了与改进的封装层形成铜互连的方法。提供基底层。覆盖衬底层的导电迹线被提供。第一金属间电介质层沉积在导电迹线上。第一金属间电介质层被蚀刻到下面的导电迹线，其中第一金属间电介质层不被光致抗蚀剂掩模保护以形成互连沟槽。沉积覆盖在第一金属间电介质层上并且暴露导电迹线的阻挡层。沉积铜层沉积在阻挡层上并填充互连沟槽。铜层和阻挡层被抛光到第一金属间电介质层的顶表面以限定铜互连。形成覆盖铜互连的封装层，其中封装层没有形成在第一金属间互连层上，其中封装层至少部分地由氮化钨组成。沉积第二金属间电介质层并完成集成电路器件的制造。

76. 发明授权

US6010962A Copper chemical-mechanical-polishing (CMP) dishing 有权
标题翻译：铜化学机械抛光（CMP）凹陷
公开(公告)号：US6010962A
公开(公告)日：2000-01-04
申请号：US249262
申请日：1999-02-12
申请人： Chung-Shi Liu , Chung-Long Chang , Chen-Hua Yu
发明人： Chung-Shi Liu , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L21/321 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76879 , H01L21/32115
摘要： A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical-mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure, however. Then the photoresist is removed from the composite structure, and replaced, in its place, with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal. In a second embodiment, the seed layer and the barrier layer are chemical-mechanical polished without first depositing a photoresist layer. Copper metal is next selectively formed by electroless plating having a dome-like protrusion, which in turn is removed by chemical-mechanical polishing without the detrimental formation of dishing in the copper metal.
摘要翻译：公开了一种用于在绝缘层中形成镶嵌铜互连的方法，而不会在多余的铜的化学机械抛光之后发生通常预期的凹陷。这通过在包括已经形成在绝缘层中的复合凹槽/孔结构的衬底上形成共形覆盖层阻挡层，然后在阻挡层上生长铜籽晶层来实现。接着在填充复合结构的基板上沉积一层光致抗蚀剂。然后通过化学机械抛光除去光致抗蚀剂层，种子层和阻挡层，然而将种子层和阻挡层留在复合结构的内壁上。然后将光致抗蚀剂从复合结构中去除，并在其位置上用化学镀铜替代，其形成从复合结构延伸的圆顶状突起。当基板进行化学机械抛光以去除多余的铜时，圆顶状结构防止铜金属的凹陷。在第二实施例中，晶种层和阻挡层在没有首先沉积光致抗蚀剂层的情况下进行化学机械抛光。接下来通过具有圆顶状突起的化学镀选择性地形成铜金属，其通过化学机械抛光而被除去，而不会有害地形成铜金属中的凹陷。

77. 发明授权

US08664040B2 Exposing connectors in packages through selective treatment 有权
标题翻译：通过选择性处理将连接器暴露在包装中
公开(公告)号：US08664040B2
公开(公告)日：2014-03-04
申请号：US13331061
申请日：2011-12-20
申请人： Chen-Hua Yu , Chung-Shi Liu , Chun-Cheng Lin , Meng-Tse Chen , Ming-Da Cheng
发明人： Chen-Hua Yu , Chung-Shi Liu , Chun-Cheng Lin , Meng-Tse Chen , Ming-Da Cheng
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/31 , H01L21/563 , H01L21/565 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L24/14 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/12042 , H01L2924/15192 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/00
摘要： A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.
摘要翻译：一种方法包括对包装进行蚀刻步骤。该包装包括包装部件，在包装部件的顶表面上的连接器，结合到包装部件的顶表面的管芯，以及模制在包装部件的顶表面上的模制材料。成型材料覆盖连接器，其中通过蚀刻步骤去除覆盖连接器的成型材料的一部分，并且连接器被暴露。

78. 发明授权

US08440562B2 Germanium-containing dielectric barrier for low-K process 有权
标题翻译：含锗介电阻挡层用于低K工艺
公开(公告)号：US08440562B2
公开(公告)日：2013-05-14
申请号：US12881939
申请日：2010-09-14
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L23/53295 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底; 半导体衬底上的第一电介质层; 第一电介质层中的导电布线; 以及导电布线上的锗锗化锗氮化物层。

79. 发明申请

US20120211547A1 In-Situ Accuracy Control in Flux Dipping 有权
标题翻译：焊剂浸渍中的原位精度控制
公开(公告)号：US20120211547A1
公开(公告)日：2012-08-23
申请号：US13031040
申请日：2011-02-18
申请人： Yi-Li Hsiao , Chen-Hua Yu , Chung-Shi Liu , Chien Ling Hwang
发明人： Yi-Li Hsiao , Chen-Hua Yu , Chung-Shi Liu , Chien Ling Hwang
IPC分类号： B23K1/20 , B23K3/08
CPC分类号： B23K1/203 , B23K3/082
摘要： A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator.
摘要翻译：焊剂浸渍装置包括具有顶表面的焊剂板; 以及在焊剂板中的浸入腔并且从顶表面凹陷。助熔剂矫正器设置在焊剂板上方并且被配置成平行于顶表面移动。压电致动器被配置为响应于施加到第一压电致动器的电极的控制电压来调节通量调节器和顶表面之间的距离。

80. 发明申请

US20120028441A1 Method and System for Bonding 3D Semiconductor Device 审中-公开
标题翻译：贴合三维半导体器件的方法和系统
公开(公告)号：US20120028441A1
公开(公告)日：2012-02-02
申请号：US13269260
申请日：2011-10-07
申请人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
发明人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
IPC分类号： H01L21/762
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/6836 , H01L21/762 , H01L21/76898 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/05553 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.
摘要翻译：一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

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