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71. 发明申请

US20080175053A1 SILICON ON INSULATOR AND THIN FILM TRANSISTOR BANDGAP ENGINEERED SPLIT GATE MEMORY 有权
标题翻译：绝缘子和薄膜晶体管上的绝缘子工程分割栅存储器
公开(公告)号：US20080175053A1
公开(公告)日：2008-07-24
申请号：US12056489
申请日：2008-03-27
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0483 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792
摘要： Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.
摘要翻译：存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

72. 发明申请

US20070029625A1 Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer 有权
标题翻译：具有氧化物 - 氧化物 - 氧化物（ONO）顶部介电层的非易失性存储器半导体器件
公开(公告)号：US20070029625A1
公开(公告)日：2007-02-08
申请号：US11197668
申请日：2005-08-04
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/792 , H01L29/513
摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.
摘要翻译：非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域源极和漏极区域之间的硅衬底。该电池包括形成在衬底的主表面上的底部氧化物层。底部氧化物层设置在靠近阱区域的主表面的一部分上。电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。电介质隧道层包括第一氧化物层，氮化物层和第二氧化物层。擦除NVM单元包括施加正栅极电压以从栅极注入孔。

73. 发明申请

US20130264683A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130264683A1
公开(公告)日：2013-10-10
申请号：US13443417
申请日：2012-04-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/00 , H01L21/56
CPC分类号： H01L23/3192 , H01L27/11565 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基极，层叠结构和掺杂层。堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和第一侧壁的长边缘沿着通道方向延伸。掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

74. 发明授权

US09240405B2 Memory with off-chip controller 有权
标题翻译：具有片外控制器的内存
公开(公告)号：US09240405B2
公开(公告)日：2016-01-19
申请号：US13089652
申请日：2011-04-19
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L27/118 , H01L27/06 , H01L27/02 , H01L27/105 , H01L27/115
CPC分类号： H01L27/0688 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.
摘要翻译：描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。然后可以将单独的电路堆叠并结合在一起。

75. 发明申请

US20120267689A1 Memory with Off-Chip Controller 有权
标题翻译：具有片外控制器的存储器
公开(公告)号：US20120267689A1
公开(公告)日：2012-10-25
申请号：US13089652
申请日：2011-04-19
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/0688 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.
摘要翻译：描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。然后可以将单独的电路堆叠并结合在一起。

76. 发明授权

US07200045B2 Method for programming a charge-trapping nonvolatile memory cell by raised-Vs channel initialed secondary electron injection (CHISEL) 有权
标题翻译：通过升高Vs通道初始化二次电子注入（CHISEL）对电荷捕获非易失性存储单元进行编程的方法
公开(公告)号：US07200045B2
公开(公告)日：2007-04-03
申请号：US11026708
申请日：2004-12-30
申请人： Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0466
摘要： A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive drain voltage is greater than the positive source voltage. The substrate of the charge-trapping nonvolatile memory cell is grounded. A positive gate voltage is applied to the polysilicon gate of the charge-trapping nonvolatile memory cell.
摘要翻译：公开了一种凸起Vs通道初始二次电子注入来对电荷捕获非易失性存储单元进行编程。电荷捕获非易失性存储单元的源极被施加正的源极电压，并且电荷俘获非易失性存储单元的漏极被施加正的漏极电压，其中正的漏极电压大于正的源极电压。电荷捕获非易失性存储单元的衬底接地。正栅极电压被施加到电荷捕获非易失性存储单元的多晶硅栅极。

77. 发明授权

US08987098B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08987098B2
公开(公告)日：2015-03-24
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

78. 发明授权

US08759899B1 Integration of 3D stacked IC device with peripheral circuits 有权
标题翻译：集成3D堆叠式IC器件与外围电路
公开(公告)号：US08759899B1
公开(公告)日：2014-06-24
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L29/788
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

79. 发明申请

US20130175598A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130175598A1
公开(公告)日：2013-07-11
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

80. 发明授权

US09082656B2 NAND flash with non-trapping switch transistors 有权
标题翻译： NAND闪存与非陷阱开关晶体管
公开(公告)号：US09082656B2
公开(公告)日：2015-07-14
申请号：US13294852
申请日：2011-11-11
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

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