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71. 发明授权

US07416935B2 Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together 有权
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件的制造方法
公开(公告)号：US07416935B2
公开(公告)日：2008-08-26
申请号：US11407242
申请日：2006-04-20
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions in the mask layer, first conductive layer, gate insulating film and semiconductor substrate; forming first trenches in parts of the first conductive layer separated by the element-isolating region; forming inter-gate insulating films on sides of each floating gate; forming control gates in the first trenches; making second trenches in parts of the mask layer and first conductive layer and in adjacent parts of the element-isolating regions; forming conductive members in the second trenches, wherein a top of the conductive members is at the same level as an upper surface of the mask layer; and removing parts of the first conductive layer and the gate insulating film exclusive of the conductive members.
摘要翻译：一种制造非易失性半导体存储器件的方法，包括在半导体衬底上形成栅绝缘膜，提供浮栅和掩模的第一导电层，在掩模层中形成多个元件隔离区，第一导电层，栅极绝缘膜和半导体衬底; 在由元件隔离区隔开的第一导电层的部分中形成第一沟槽; 在每个浮动栅极的侧面形成栅极间绝缘膜; 在第一沟槽中形成控制栅极; 在掩模层和第一导电层的部分以及元件隔离区的相邻部分中形成第二沟槽; 在所述第二沟槽中形成导电构件，其中所述导电构件的顶部处于与所述掩模层的上表面相同的水平; 以及去除不包括导电构件的第一导电层和栅极绝缘膜的部分。

72. 发明申请

US20060060911A1 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 失效
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件
公开(公告)号：US20060060911A1
公开(公告)日：2006-03-23
申请号：US10988534
申请日：2004-11-16
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semiconductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.
摘要翻译：一种半导体存储器件，包括半导体衬底，设置在衬底上的多个单元晶体管，设置在衬底上的多个选择栅极以及设置在单元晶体管之间和选择栅极之间的元件隔离区域。每个单元晶体管具有设置在设置在基板上的栅极绝缘膜上的浮置栅极，设置在基板中并与浮置栅极的侧对准的源极和漏极，设置在浮置栅极的一侧的栅极间绝缘膜以及设置在栅极间绝缘膜上并铺设在浮动栅极的一侧上的控制栅极。选择栅极由设置在栅极绝缘膜上并嵌入选择栅极的导电构件连接。

73. 发明授权

US09293547B2 NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps 有权
标题翻译：具有垂直气隙的NAND EEPROM和用于制造具有垂直气隙的NAND EEPROM的方法
公开(公告)号：US09293547B2
公开(公告)日：2016-03-22
申请号：US13237425
申请日：2011-09-20
申请人： Fumitaka Arai , Wataru Sakamoto , Fumie Kikushima , Hiroyuki Nitta
发明人： Fumitaka Arai , Wataru Sakamoto , Fumie Kikushima , Hiroyuki Nitta
IPC分类号： H01L29/788 , H01L21/28 , H01L29/792 , H01L29/423 , H01L21/764 , H01L27/115 , H01L29/66 , H01L21/762 , H01L21/768 , H01L21/8234
CPC分类号： H01L29/42336 , H01L21/76224 , H01L21/764 , H01L21/7682 , H01L21/823481 , H01L27/115 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L29/66825 , H01L29/788 , H01L29/7881
摘要： According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.
摘要翻译：根据一个实施例，去除埋在沟槽中的埋入绝缘膜的一部分; 因此，在字线方向上在相邻的浮置栅电极之间形成气隙，并且沿着沟槽以沉没在控制栅电极下方的方式连续地形成气隙。

74. 发明授权

US08829623B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08829623B2
公开(公告)日：2014-09-09
申请号：US12248483
申请日：2008-10-09
申请人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
发明人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
IPC分类号： H01L27/088 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11526
摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.
摘要翻译：根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

75. 发明授权

US08541830B1 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08541830B1
公开(公告)日：2013-09-24
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

76. 发明授权

US08377814B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08377814B2
公开(公告)日：2013-02-19
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

77. 发明授权

US08223558B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08223558B2
公开(公告)日：2012-07-17
申请号：US13179714
申请日：2011-07-11
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

78. 发明申请

US20120126306A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件的非易失性存储器件和制造方法
公开(公告)号：US20120126306A1
公开(公告)日：2012-05-24
申请号：US13238380
申请日：2011-09-21
申请人： Genki KAWAGUCHI , Fumitaka Arai , Satoshi Nagashima , Naoki Kai , Wataru Sakamoto , Hiroyuki Nitta
发明人： Genki KAWAGUCHI , Fumitaka Arai , Satoshi Nagashima , Naoki Kai , Wataru Sakamoto , Hiroyuki Nitta
IPC分类号： H01L29/788 , H01L21/28 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/764 , H01L21/7682 , H01L27/11529 , H01L29/42376
摘要： According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.
摘要翻译：根据一个实施例，存储单元包括电荷存储层。在字线方向相邻的电荷存储层之间设置第一气隙。在位线方向相邻的电荷存储层之间提供第二气隙。

79. 发明申请

US20120069669A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING AND MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储装置及其控制和制造方法
公开(公告)号：US20120069669A1
公开(公告)日：2012-03-22
申请号：US13237320
申请日：2011-09-20
申请人： Wataru SAKAMOTO , Fumitaka Arai
发明人： Wataru SAKAMOTO , Fumitaka Arai
IPC分类号： G11C16/10 , H01L21/762
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/10 , G11C16/3418 , H01L21/28273 , H01L27/11524
摘要： A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage.
摘要翻译：公开了一种非易失性半导体存储装置。该设备包括具有第一存储器单元的单元组和位于第一定向相邻于第一存储单元的第二存储单元，以及编程电路。第一存储单元用于数据保持，第二存储单元用于调整第一存储单元的阈值电压。编程电路被配置为通过向第二存储器单元施加电压来对第一存储单元进行编程，以将第一存储单元的阈值电压控制为高于第一阈值电压。

80. 发明授权

US08120092B2 Semiconductor memory device and manufacturing method therefor 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08120092B2
公开(公告)日：2012-02-21
申请号：US12565181
申请日：2009-09-23
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

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