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71. 发明申请

US20120161204A1 Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy 有权
标题翻译：晶体管包括嵌入式西格玛形成的顺序形成的半导体合金
公开(公告)号：US20120161204A1
公开(公告)日：2012-06-28
申请号：US13232571
申请日：2011-09-14
申请人： Stefan Flachowsky , Jan Hoentschel , Stephan-Detlef Kronholz , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Stephan-Detlef Kronholz , Thilo Scheiper
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
摘要翻译：在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性晶体管在其处理期间。例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。

72. 发明申请

US20110104863A1 TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SACRIFICIAL CARBON SPACER 有权
标题翻译：包括在基于碳酸盐空间的排水/源区域形成的高K金属电极结构的晶体管
公开(公告)号：US20110104863A1
公开(公告)日：2011-05-05
申请号：US12894579
申请日：2010-09-30
申请人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
发明人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
IPC分类号： H01L21/336
CPC分类号： H01L21/28238 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/51 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.
摘要翻译：当在早期制造阶段形成复杂的高k金属栅电极结构时，可以基于碳间隔元件有效地去除栅电极结构的电介质盖层，这可以保持氮化硅间隔结构的完整性。此后，可以基本上除去牺牲碳隔离物而不影响其它器件区域，例如隔离结构，有源区等，这可能有助于在半导体器件的进一步处理期间优良的工艺条件。

73. 发明授权

US08987104B2 Method of forming spacers that provide enhanced protection for gate electrode structures 有权
标题翻译：形成对栅电极结构提供增强保护的间隔物的方法
公开(公告)号：US08987104B2
公开(公告)日：2015-03-24
申请号：US13108363
申请日：2011-05-16
申请人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
发明人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/78618 , H01L29/78687
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区，其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区，位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物，和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

74. 发明授权

US08936977B2 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权
标题翻译：在28nm低功率/高性能技术上使用硅氧化物封装，早期晕圈和延伸注入的PMOS器件的晚期原位掺杂SiGe结
公开(公告)号：US08936977B2
公开(公告)日：2015-01-20
申请号：US13482393
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L21/338
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
摘要翻译：提供具有PMOS eSiGe源极/漏极区域的HKMG器件。实施例包括在衬底上形成第一和第二HKMG栅极堆叠，在每个HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物衬垫，在每个HKMG栅极堆叠的每一侧执行卤素/延伸注入，形成氧化物衬垫和氮化物衬垫在每个HKMG栅极堆叠的氧化物间隔物上，在第二HKMG栅极堆叠的相对侧形成深的源极/漏极区域，在第二HKMG栅极堆叠层上形成氧化物硬掩模，在第一金属间化合物栅极堆叠的相对侧形成嵌入的硅锗（eSiGe） HKMG栅极堆叠，并去除氧化物硬掩模。

75. 发明授权

US08790973B2 Workfunction metal stacks for a final metal gate 有权
标题翻译：用于最终金属门的功能金属堆叠
公开(公告)号：US08790973B2
公开(公告)日：2014-07-29
申请号：US13445475
申请日：2012-04-12
申请人： Thilo Scheiper , Jan Hoentschel
发明人： Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.
摘要翻译：在栅极图案化之后，晶体管器件由具有基本相等厚度的pMOS和nMOS功函数堆叠形成。实施例包括在基板中形成n型和p型区域，在两个区域上形成pMOS功函数金属堆叠层，在n型区域上的pMOS功函数金属堆叠层上形成硬掩模层，去除pMOS功函数金属堆层，在p型区域和硬掩模层上形成nMOS功函数金属堆叠层，并从硬掩模层去除nMOS功函数金属堆叠层。

76. 发明授权

US08664068B2 Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications 有权
标题翻译：用于低功耗/高性能应用的CMOS晶体管中的低扩散漏极和源极区域
公开(公告)号：US08664068B2
公开(公告)日：2014-03-04
申请号：US13192620
申请日：2011-07-28
申请人： Jan Hoentschel , Stefan Flachowsky , Steven Langdon , Thilo Scheiper
发明人： Jan Hoentschel , Stefan Flachowsky , Steven Langdon , Thilo Scheiper
IPC分类号： H01L21/336 , H01L21/36
CPC分类号： H01L21/823807 , H01L21/823814
摘要： The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.
摘要翻译：漏极和源极区域可以至少部分地由原位掺杂的外延生长的半导体材料形成，用于为低功率和高性能应用设计的复杂半导体器件中的互补晶体管。为此，空穴可以用原位掺杂的半导体材料重新填充，在一些说明性实施例中，还可以在互补晶体管的沟道区域中提供期望的应变。

77. 发明授权

US08609533B2 Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts 有权
标题翻译：具有基板触点的集成电路的制造方法和具有基板触点的集成电路
公开(公告)号：US08609533B2
公开(公告)日：2013-12-17
申请号：US13436323
申请日：2012-03-30
申请人： Thilo Scheiper , Stefan Flachowsky , Jan Hoentschel
发明人： Thilo Scheiper , Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/311 , H01L21/314 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译：提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。在由第一沟槽暴露的硅衬底中形成金属硅化物区域。第一应力诱导层形成在金属硅化物区域之上。第二应力诱导层形成在第一应力诱导层上。介电材料的ILD层形成在第二应力诱导层上。形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。第二沟槽填充有导电材料。

78. 发明申请

US20130323892A1 METHODS OF PERFORMING HIGHLY TILTED HALO IMPLANTATION PROCESSES ON SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件上执行高度倾斜的HALO植入工艺的方法
公开(公告)号：US20130323892A1
公开(公告)日：2013-12-05
申请号：US13487351
申请日：2012-06-04
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
摘要翻译：本文公开的一种说明性方法包括分别形成包括用于第一晶体管器件和第二晶体管器件的帽层的第一和第二栅极结构，其中第一和第二晶体管彼此横向取向，执行第一晕圈离子注入工艺以形成第一晶体管的第一晕环注入区，其中盖层位于第一晶体管的第一栅极结构中的位置，从至少第二晶体管的第二栅极结构去除覆盖层，并且在去除覆盖层之后，执行第二晕圈离子注入工艺以形成用于第二晶体管的第二晕环注入区，其中第一和第二晕环注入工艺以相对于衬底的横向角度进行。

79. 发明授权

US08598007B1 Methods of performing highly tilted halo implantation processes on semiconductor devices 有权
标题翻译：在半导体器件上执行高度倾斜的晕圈注入工艺的方法
公开(公告)号：US08598007B1
公开(公告)日：2013-12-03
申请号：US13487351
申请日：2012-06-04
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
摘要翻译：本文公开的一种说明性方法包括分别形成包括用于第一晶体管器件和第二晶体管器件的帽层的第一和第二栅极结构，其中第一和第二晶体管彼此横向取向，执行第一晕圈离子注入工艺以形成第一晶体管的第一晕环注入区，其中盖层位于第一晶体管的第一栅极结构中的位置，从至少第二晶体管的第二栅极结构去除覆盖层，并且在去除覆盖层之后，执行第二晕圈离子注入工艺以形成用于第二晶体管的第二晕环注入区，其中第一和第二晕环注入工艺以相对于衬底的横向角度进行。

80. 发明申请

US20130313572A1 SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF 有权
公开(公告)号：US20130313572A1
公开(公告)日：2013-11-28
申请号：US13953349
申请日：2013-07-29
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L29/78 , H01L29/16
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

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