专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US6153910A Semiconductor device with nitrogen implanted channel region 失效
标题翻译：具有氮注入沟道区的半导体器件
公开(公告)号：US6153910A
公开(公告)日：2000-11-28
申请号：US940400
申请日：1997-10-01
申请人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
发明人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/772 , H01L29/76
CPC分类号： H01L21/26506 , H01L29/1033 , H01L29/105 , H01L29/66575
摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
摘要翻译：在硅衬底的表面上形成硼扩散区。在硼扩散区的表面形成一对n型源/漏区。在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。由此，可以获得容易小型化的晶体管结构。

72. 发明授权

US5837606A Semiconductor device having internal wire and method of fabricating the same 失效
公开(公告)号：US5837606A
公开(公告)日：1998-11-17
申请号：US668012
申请日：1996-06-17
申请人： Takehisa Yamaguchi , Hidekazu Oda
发明人： Takehisa Yamaguchi , Hidekazu Oda
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8244 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/11 , H01L21/4763
CPC分类号： H01L27/1112 , H01L23/53257 , H01L27/11 , H01L2924/0002
摘要： In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

73. 发明授权

US5683923A Semiconductor memory device capable of electrically erasing and writing information and a manufacturing method of the same 失效
标题翻译：能够电擦除和写入信息的半导体存储器件及其制造方法
公开(公告)号：US5683923A
公开(公告)日：1997-11-04
申请号：US480701
申请日：1995-06-07
申请人： Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
发明人： Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.
摘要翻译：半导体存储器件及其制造方法可以有效地防止在数据擦除操作中可能发生的耐久特性的劣化，以及在数据写入操作中可能发生的漏极干扰现象。在半导体存储器件中，在位于沟道区域中的P型硅衬底1的主表面上形成N型杂质层3。因此，在擦除数据期间，不向N型杂质层3和N型源极扩散区域10之间的边界区域施加高电场，从而有效地防止了在该区域产生带间隧穿。另外，在该半导体存储器件中，漏极扩散区域9具有偏移结构，其中没有任何部分与浮置栅极电极5重叠。因此，在浮置栅极电极5和漏极扩散区域9两端产生的电场与现有技术相比，写入数据期间的未选择的单元被削弱，并且有效地防止了由于FN隧穿引起的漏极干扰现象。

74. 发明授权

US5428235A Semiconductor memory device including improved connection structure to FET elements 失效
标题翻译：半导体存储器件包括改进的与FET元件的连接结构
公开(公告)号：US5428235A
公开(公告)日：1995-06-27
申请号：US300878
申请日：1994-09-06
申请人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
发明人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposedand second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode. It is possible to provide a field effect transistor in which increase in speed can be realized and to provide a semiconductor memory device in which capacitance of the capacitor can be sufficiently secured in case of making miniaturization of the memory cell. It is also possible to prevent decrease in reliability caused by disconnection of the bit line.
摘要翻译： DRAM的存储单元包括一个MOS晶体管和一个电容器。 MOS晶体管包括一对源极/漏极区域和形成在沟道区域上的栅极电极。形成位线以便连接到源极/漏极区域。导电层形成为连接到源/漏区。栅电极包括形成在沟道区上的第一部分，其中介于氧化膜之间，第二和第三部分分别从第一部分延伸并且形成在位线上，并且导电层被插入夹层氧化膜。电容器包括形成为连接到导电层的下电极和形成为与介电膜插入的下电极的表面相对的上电极。上电极位于位线上方。字线放置在上电极上方并连接到栅电极。可以提供一种可以实现速度增加的场效应晶体管，并且提供一种在使存储单元小型化的情况下能够充分确保电容器的电容的半导体存储器件。也可以防止由位线的断线引起的可靠性降低。

75. 发明授权

US5218217A Dynamic random access memory device and method of manufacturing 失效
标题翻译：动态随机存取存储器件及其制造方法
公开(公告)号：US5218217A
公开(公告)日：1993-06-08
申请号：US568567
申请日：1990-08-16
申请人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
发明人： Hidekazu Oda , Kiyoteru Kobayashi , Takehisa Yamaguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/786
CPC分类号： H01L27/10802 , H01L27/10805 , H01L29/78654
摘要： Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film. Reduced surface area occupied by each memory cell comprising a field effect transistor and a capacitor enables miniaturization of the memory cell. Electric charges generated by the impact ionization phenomenon are stored in the capacitor, so that a power consumed in a writing operation of data can be reduced.
摘要翻译：动态随机存取存储器的每个存储单元包括第一导电类型的半导体层，第二导电类型的一个和另一个杂质区，第一导电类型的栅电极，电容器杂质区和电容器电极。第一导电类型的半导体层包括第一表面和与第一表面相对的第二表面。在半导体层中形成彼此间隔开的一个和其它杂质区，以便限定沟道区，其中沟道表面是半导体层的第一表面的一部分。栅电极通过栅极绝缘膜形成在沟道表面上。在半导体层的第二表面附近形成与沟道区相对的电容器杂质区，其浓度高于半导体层的浓度。电容器电极通过电介质膜形成在电容器杂质区上。由包括场效应晶体管和电容器的每个存储单元占用的减小的表面积使得能够使存储单元小型化。由电击现象产生的电荷存储在电容器中，从而可以减少数据写入操作中消耗的功率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式